summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Expand)Author
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
2014-12-16tegra124: Always enable DC when attaching SOR.Hung-Te Lin
2014-12-16nyan*: debug: Add sor registers dump functionJimmy Zhang
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
2014-12-16nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 registerJimmy Zhang
2014-12-16nyan*: merge a couple of sor setting difference from kernel driverJimmy Zhang
2014-12-16nyan*: Apply sor fix from kernel dc driverJimmy Zhang
2014-12-16tegra124: Initialize display panel by EDID.Hung-Te Lin
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
2014-12-16i2c: Replace the i2c API.Gabe Black
2014-12-15tegra124: set MOT bit for I2C-over-AUXKen Chang
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
2014-12-15tegra124: Release DMA channel at end of transactionDavid Hendricks
2014-12-15tegra124: Use correct mask for APB bus widthDavid Hendricks
2014-12-15nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.Gabe Black
2014-12-15tegra124: More improvements to the clock initialization macros.Gabe Black
2014-12-15tegra: spi: Read the command1 register to ensure the write to it completes.Gabe Black
2014-12-15tegra124: A couple clock fixes.Gabe Black
2014-12-15tegra124: Add tegra_dc_i2c_aux_read to allow reading EDID.Hung-Te Lin
2014-12-15tegra124: Skip display init when vboot says we don't need it.Gabe Black
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
2014-12-09UCB RISCV: Switch to DYNAMIC_CBMEMKyösti Mälkki
2014-12-09fsp platfoms: add prototype & consolidate main entry-pointMartin Roth
2014-12-08intel/baytrail: Spelling fixesMartin Roth
2014-12-08intel/fsp_baytrail: Spelling fixesMartin Roth
2014-12-08samsung/exynos5420: Spelling FixesMartin Roth
2014-12-08intel/broadwell: Spelling fixesMartin Roth
2014-12-06soc/qualcomm/ipq806x/Kconfig: Fix indent styleEdward O'Callaghan
2014-12-05fsp_baytrail: Update function disable codeMartin Roth
2014-12-05fsp_baytrail: Kconfig update for Gold 3 FSPMartin Roth
2014-12-05fsp_baytrail: Update microcode for Gold 3 FSP releaseMartin Roth
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
2014-12-05ipq8064: Make clock code build in corebootVadim Bendebury
2014-12-05ipq8064: prepare UART driver for use in corebootVadim Bendebury
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
2014-12-05fsp_baytrail: update printk to use FSP_INFO_LEVELMartin Roth
2014-12-05fsp_baytrail: update for UPD_DEVICE_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update for UPD_SPD_CHECK macroMartin Roth
2014-12-05fsp_baytrail: update to add the UPD_DEFAULT_CHECK macroMartin Roth
2014-12-02Replace hlt with halt()Patrick Georgi
2014-12-01Add UCB RISCV support for architecture, soc, and emulation mainboard..Ronald G. Minnich
2014-12-01Mark non-executable files non-executablePatrick Georgi
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 23:38:16 +0000