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Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5
and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team.
Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL
is defined in the dptf.asl.
BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot and booted on nami board.
Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25614
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Also base the FSP/GOP related bail-out on the correct Kconfig option
to allow adding a VBT along with libgfxinit.
Most things should work, what doesn't is backlight control because
coreboot misses the settings (moved to FSP and need backporting).
Also, Kaby Lake is still unsupported.
TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with
text and linear framebuffer mode and viewed a FILO menu.
Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This makes FSP use the same baud rate as coreboot so that the user can
more easily change it without having to modify the FSP binary.
Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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APL and GLK have 39 address bits
Change-Id: I9b761492332c545c13a0594d8f5937ca84bc0699
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.
BUG=b:72728953
Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system with the latest microcode version.
The hang occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.
Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.
To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.
This issue is known already and was discussed on the mailinglist:
[coreboot] BDX-DE PCI init fail
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html
TEST=Boot mc_bdx1 with microcode version M1050663_07000012.
Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25652
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.
This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.
There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
decoding the serial number into a byte array.
google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.
Testing this on grunt, dmidecode now shows the full serial number:
Serial Number: 00000000
BUG=b:65403853
TEST=tested on grunt
Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The converter was setting SMBIOS values when dimm_info expects SPD
values.
dmidecode now shows the following:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 933 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 933 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Example debug output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): ' 00000000'
PartNumber(20): 'HMAA51S6AMR6N-UH '
CBMEM_ID_MEMINFO:
dimm_size: 8192
ddr_type: 0x1a
ddr_frequency: 933
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x4
bus_width: 3
serial: 0x00000000
module_part_number(18): 'HMAA51S6AMR6N-UH '
The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.
`mosys memory spd print all` is still failing though. I will look into
that next.
BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above
Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts")
Change-Id: I5730259bc6819defc482d31644e1f476679257b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25588
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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To avoid rounding errors with the current data types, the formula in
this function must be converted.
Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This is required for clock parameter settings to take effect.
BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz
Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I639be58df358129c1f420cf8d1540edd408859a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB
This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.
Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.
TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.
Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On APL and GLK the i2c blocks use 133MHz input clock, but the
SPI blocks use a 100MHz input clock. Fix this so that the proper
target frequencies can be hit on the SPI controllers.
BUG=b:75306520
Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.
BUG=b:75306520
Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As part of moving AGESA calls from bootblock to romstage, callback function
AGESA_HALT_THIS_AP must be available at romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: I0992b2de5856881c19191ec4f637168727686524
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25527
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:77605178
TEST=Tested EC wake sources
Change-Id: Id879b3e91d4c0794662cf3d8204bd077117db23c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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MONITOR/MWAIT had an irremediable hardware bug for Apollolake.
This has been fixed for GLK. Therefore, make MONITOR/MWAIT based
C-states the default for GLK and disable IO-Redirection based
C-states used for Apollolake.
Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state
residencies with and without load.
Tested for S0ix entry and exit using:
"echo freeze > /sys/power/state" and "suspend_stress_test -c 500".
BUG=b:77639897
Change-Id: If648c25a9b26c04b278dce4af241d439790288ca
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/19718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add function to modify NXE bit & PAT.
BUG=None
BRANCH=None
TEST=Make sure build for Glkrvp is successful.
Change-Id: I265d6d5ca538496934a375eb8d99d52879522051
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25480
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.
BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.
Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move flush_l1d_l2 function to common location within the SoC.
BUG=None:
BRANCH=None
TEST= Build for glkrvp.
Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Broadwell-DE the FSP sets up DCACHE in the early call. The address
does not match the default FSP 1.0 address defined in
src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range
is used in pre-ramstage stages.
This patch provides the matching DCACHE_RAM_BASE value among with a
suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation.
The include order of Kconfig files makes sure that the Kconfig file in
the soc directory is sourced first and the defined values will override
the ones in src/drivers/intel/fsp1_0/Kconfig.
Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Provide ACPI path names for PCI domain and LPC device so that generated
ACPI tables have valid device paths.
Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Convert agesa_heap_base() to static since it's unused outside of
heapmanager.c.
Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Replace an absolute value with a #define value in bootblock. This is
in preparation for using an additional MTRR in a subsequent patch.
Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Add FSP option to enable/disable VT-d (Intel Virtualization Technology
for Directed I/O) and VMX (Virtual Machine Extensions), VMX will be
disabled once VT-d got disabled.
Bug=b:73655383
TEST=Build and flash image on meowth board with debug build FSP, in
serial log search for "VMXEnable" and "VtdDiable".
Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by kernel when boot source is not
EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to
cover cases that the system doesn't boot from EMMC.
BUG=b:76202699
TEST=Install OS into EMMC
Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.
BUG=b:72875858
TEST=Build Gardenia.
Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Initialize 1st 4GB as Device Memory, except:
* 1st page: NULL address
* System_IMEM: Cached SRAM
* Boot_IMEM: Cached SRAM
TEST=build
Change-Id: Ic6cf022b08bb2568fdf956cea8bad46da89236c5
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25201
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Removed 33KB hole in SSRAM
TEST=build & run
Change-Id: I6851860f878d9a0688975fa855980870d657ee1a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25391
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers (maybe, who knows, the blob is undocu-
mented), advertised to FSP and reserved from the OS.
The new devicetree option `ignore_vtd` allows to retain the old beha-
viour (do whatever pre-set UPD values suggest).
We also let FSP set up distinct BDFs for messages originating from the
I/O-APIC and the HPET.
Change-Id: I77f87c385736615c127143760bbd144f97986b37
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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Sometimes when bringing up a new board it can take a while until you
have all the peripheral drivers ready. For those cases it is nice to be
able to bitbang certain protocols so that you can already get further in
the boot flow while those drivers are still being worked on. We already
have this support for I2C, but it would be nice to have something for
SPI as well, since without SPI you're not going to boot very far.
This patch adds a couple of helper functions that platforms can use to
implement bit-banging SPI with minimal effort. It also adds a proof of
concept implementation using the RK3399.
Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The <gpio.h> API is supposed to include a gpio_set() function that just
toggles the state of a GPIO already configured as an output, even though
we rarely need it since gpio_output() can already be used to initialze a
GPIO to a default value while configuring it as an output. This function
was forgotten on Rockchip, so this patch adds it now.
Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:77345148
TEST=Pull power from grunt, verify CMOS power failure is detected.
Reboot and verify that CMOS power failure is not detected.
Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.
Implementation modeled on existing Baytrail code.
Test: boot Windows 10 on google/chell with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.
Implementation modeled on existing Baytrail code.
Test: boot Windows 10 on google/edgar with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.
Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.
Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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me_progress_rom_values array provides detailed information maps to ME
HFSTS2 register value.
There is a chance that ME status value might be over the size of
me_progress_rom_values.
This commit adds a check before access the array.
BUG=b:77247550
Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/25425
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable VMX if supported by CPU and enabled in board devicetree.
Check lock bit unset before enabling VMX.
Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.
Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
Change-Id: I5aea15511c52d1191babf551feb237f4144683e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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