coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-10	soc/amd/picasso: Add MADT entry for GNB IOAPIC	Jason Glenesk
2020-09-10	soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP	Marshall Dawson
2020-09-10	soc/mediatek: Drop unneeded empty lines	Elyes HAOUAS
2020-09-10	soc/intel/alderlake: Rename pch_init() code	Subrata Banik
2020-09-10	soc/intel/tigerlake: Maintain consistent tab in iomap.h	Subrata Banik
2020-09-10	sc7180: Add display hardware pipe line initialization	Vinod Polimera
2020-09-10	sc7180: Add display dsi interface programming	Vinod Polimera
2020-09-10	sc7180: enable bl31	T Michael Turney
2020-09-09	soc/intel/common/block/imc: Drop unused code	Angel Pons
2020-09-09	sc7180: Add display 10nm phy & pll programming support	Vinod Polimera
2020-09-09	sc7180: clock: Add display external clock in coreboot	Taniya Das
2020-09-09	trogdor: Change Memlayout to increase QcLib region from 512 to 596kB	Ashwin Kumar
2020-09-09	trogdor: SoC makefile blob support	ashk
2020-09-09	soc/ti/am335x: Fix MLO build	Sam Lewis
2020-09-09	soc/intel/common/block/uart/Kconfig: Drop unused symbols	Angel Pons
2020-09-09	soc/intel/xeon_sp: Select CPU_INTEL_COMMON	Angel Pons
2020-09-09	soc/intel/cannonlake: Add PCIe ports on PCH-H	Patrick Rudolph
2020-09-09	apollolake: Define MAX_CPUS at SoC scope	Angel Pons
2020-09-09	geminilake: Factor out MAX_CPUS value	Angel Pons
2020-09-09	soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol	Angel Pons
2020-09-09	vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332	Subrata Banik
2020-09-08	pci_ids: Add Alder Lake DTT PCI IDs	Subrata Banik
2020-09-08	pci_ids: Add Alder Lake IPU PCI IDs	Subrata Banik
2020-09-08	soc/mediatek/mt8192: Add SPI flash controller dual read function	CK Hu
2020-09-08	soc/intel/baytrail: Add missing GSM size definitions	Angel Pons
2020-09-08	soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE'	Elyes HAOUAS
2020-09-08	soc/intel/tigerlake: Skip GPIO configuration from FSP	Srinidhi N Kaushik
2020-09-08	soc/intel/elkhartlake: Update SA & PM related definitions	Tan, Lean Sheng
2020-09-08	soc/intel/elkhartlake: Update PMC related register definitions	Tan, Lean Sheng
2020-09-08	soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table	Tan, Lean Sheng
2020-09-08	soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake	Tan, Lean Sheng
2020-09-08	soc/intel/elkhartlake: Do initial SoC commit till ramstage	Tan, Lean Sheng
2020-09-08	soc/intel/apollolake: Hook up ENABLE_VMX	Angel Pons
2020-09-08	soc/intel/apollolake: Select CPU_INTEL_COMMON	Angel Pons
2020-09-08	soc/intel/broadwell: Drop `gpu_panel_port_select`	Angel Pons
2020-09-08	soc/intel/tigerlake: Add SMRR Locking support	Tim Wawrzynczak
2020-09-08	soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP	Tim Wawrzynczak
2020-09-08	soc/mediatek/mt8192: Add SPI flash controller DMA read function	CK Hu
2020-09-06	soc/intel/apl: Add panel power and backlight configuration	Nico Huber
2020-09-06	soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default	Michael Niewöhner
2020-09-05	soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik
2020-09-04	soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO...	Elyes HAOUAS
2020-09-04	soc/intel/cnl: Enable HECI3 depending on devicetree	Felix Singer
2020-09-04	soc/intel/tigerlake: Remove unused PID_SDX macro	Subrata Banik
2020-09-03	soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.	Jason Glenesk
2020-09-03	soc/amd/picasso: Set max_speed_mts and configured_speed_mts	Rob Barnes
2020-09-03	soc/intel/cnl: Allow using the remaining Comet Lake FSPs	Felix Singer
2020-09-03	3rdparty/fsp: Update submodule pointer to current master	Felix Singer
2020-09-03	soc/intel/cnl: Add new Kconfig option which matches its FSPs name	Felix Singer
2020-09-03	soc/amd/picasso: Only build PSP bootloader & verstage into RO	Martin Roth