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2019-09-10mediatek/mt8183: Add new option for eMCP DDRHuayang Duan
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbs) while those with discrete DRAM can only run at 3200Mbps. A new option MT8183_DRAM_EMCP is added to Kconfig for a mainboard to select, depending on whether it supports eMCP or not. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-10soc/intel/skylake: Add option to toggle Hyper-ThreadingPatrick Rudolph
Tested on Supermicro X11SSH-TF. Change-Id: I3ebab68ff868c78105bb4b35abffb92f3ccf1705 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-09soc/amd/picasso: Update TSC and monotonic timerMarshall Dawson
Picasso's TimeStamp Counter is a new design and different than Stoney Ridge. Although advertised as invariant, the ST TSC did not become so until midway through POST making it an unreliable source for measuring time. This is not the case for Picasso. Remove the Stoney Ridge monotonic timer code and rely on the TSC. Modify the calculation used in Family 15h of finding the number of boost states first, and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09soc/amd/common/lpc: Add decode disable functionMarshall Dawson
It is already trivial to set D14F3x44 to 0, but add a function to wipe both that and the settings in D14F3x48, along with x48's associated addresses. Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09soc/amd/common: Add missing stdint.h to lpc.hMarshall Dawson
Include the file containing the typedefs for uint_*. Change-Id: If33765b6dc4236c4b38860bfc4f2cef9b226b81d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-09-09intel/fsp_broadwell_de: Add early timestampsKyösti Mälkki
Modify intel/fsp_broadwell_de such that timestamp_init() is before raminit (and CAR teardown of FSP1.0), adding two new early timestamps while doing so. Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already do it this way. Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09intel/fsp_broadwell_de: Enable CONSOLE_CBMEM by defaultKyösti Mälkki
In the very early days of FSP 1.0 this did not work so we kept it disabled. Change-Id: I8a88be6df335598d4c6007a8b7ff307b293e1f97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-09soc/intel/common/block/cse: Add helper function heci_send_receiveSridhar Siricilla
Aggregate sending and receiving HECI messages into a single function. TEST=Verified sending and receiving reply HECI message on CML RVP & Hatch board Change-Id: Ic95239eef8591d3aadf56a857c97f3f1e12b16ac Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35224 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-09soc/intel/cannonlake: Allow coreboot to handle SPI lockdownSubrata Banik
This patch disables FSP-S SPI lockdown UPDs and lets coreboot perform SPI lockdown (i.e.flash register DLOCK, FLOCKDN, and WRSDIS before end of post) in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-09soc/intel/cannonlake: Add ability to disable Heci1Bora Guvendik
Decide if HECI1 should be hidden prior to boot to OS. BUG=none TEST=Boot to OS, verify if Heci1 is disabled on hatch system using FSP 1344. Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-09-06soc/amd/common: Add missing stdint.h to acpimmio.hMarshall Dawson
Include the file containing the typedefs for uint_*. Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35268 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06soc/amd/common: Add missing stdint.h to BiosCallOuts.hMarshall Dawson
Include the file containing the typedefs for uint_*. Change-Id: Ib0eea9bfd0c8d9e3eba257b561980accf5b4bab4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35267 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov
This patch adds Lewisburg C62x Series PCH support by adding the Production and Super SKUs of the following PCI devices: - LPC or eSPI Controllers, - PCI Express Root Ports, - SSATA and SATA Controllers, - SMBus, - SPI Controller, - ME/HECI, - Audio, - P2SB, - Power Management Controller. These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-09-06soc/mediatek: Fix USB enumeration issueChangqi Hu
Some USB 3.0 devices fail to be enumerated after USB reset, and xhci port status register shows the device is disconnected. After measuring the USB signal, we found that the USB disconnect threshold was lower and that the disconnect event was triggered unexpectedly. USB designers suggest changing discth to 15. BUG=b:122047652 TEST=emerge-kukui coreboot chromeos-bootimage Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Signed-off-by: Changqi Hu <changqi.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-05soc/intel/cannonlake: memory spd data debugEric Lai
Add printing SPD data for debug usage. BUG=b:139397313 BRANCH=N/A TEST=Tested the on Hatch and checked cbmem log. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-04mediatek/mt8183: postpone dcxo low power mode settingWeiyi Lu
Consider the association between modem[1] and DCXO, this patch is a fix for eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [2] We should not disable XO_CEL and block the bblpm request when modem is still ON. For power-saving, we still could disable unused XO_CEL and mask request to disable unused power mode when modem is no longer be used. [1] https://review.coreboot.org/c/coreboot/+/32666 [2] https://review.coreboot.org/c/coreboot/+/32323 BRANCH=none TEST=Boots correctly on Krane. Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-03soc/skylake: do not rely on P2SB data to generate DRHDAngel Pons
The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, define them as macros and use these values directly to generate the DRHD. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-03soc/intel/common/timer: Fix cosmetic errors as per CB:35148 reviewSubrata Banik
BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: I341eec13d275504545511904db0acd23ad34e940 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35234 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-03soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensorsSumeet Pawnikar
Add fan based active cooling for TSR sensors temperature range. BUG=b:138966929 BRANCH=None TEST=Verified Fan control functionality for TSR sensors on Hatch. Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-02soc/intel/common/timer: Make TSC frequency calculation dynamicallySubrata Banik
tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02soc/skylake: prevent null pointer dereferencesAngel Pons
Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-02soc/intel/quark: Remove variable set but not usedElyes HAOUAS
Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32912 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02soc/intel/skylake: enable GMM in devicetreeMaxim Polyakov
Enables Gaussian Mixture Model (GMM) only if the corresponding pci device is enabled in the device tree Tested on Asrock H110M DVS motherboard Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-02mediatek/mt8183: Remove unnecessary parenthesesYu-Ping Wu
Parentheses are unnecessary for conditions like '(a == b) || (c == d)'. Change-Id: I0c554bf1577b40286f7a51a8fc5804bdbb7c8bd1 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35142 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02security/intel: Add TXT infrastructurePatrick Rudolph
* Add Kconfig to enable TXT * Add possibility to add BIOS and SINIT ACMs * Set default BIOS ACM alignment * Increase FIT space if TXT is enabled The following commits depend on the basic Kconfig infrastructure. Intel TXT isn't supported until all following commits are merged. Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-08-30ipq40xx: Increase CBFS and RAMSTAGE sizeKan Yan
Increase CBFS and RAMSTAGE size to accommodate larger binary component. BUG=b:77641795 TEST=Build and test on Gale. BRANCH=none Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0 Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1366388 Original-Reviewed-by: Zhihong Yu <zhihongyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35134 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30soc/intel/skl/acpi: add description for missing PCIe portsMaxim Polyakov
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, ACPI contains a description for only 12 ports. This patch adds ACPI code for missing ports [1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN [2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003 [3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30soc/intel/skylake: Remove duplicated PCI IdMaxim Polyakov
Removes PCI_DEVICE_ID_INTEL_SKL_ID_DT because this PCI Id duplicates PCI_DEVICE_ID_INTEL_SKL_ID_S_4 (0x191f) Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30arm64: Rename arm_tf.c/h to bl31.c/hJulius Werner
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h, respectively. That name is closer to the terminology used in most functions related to Trusted Firmware, and it removes the annoying auto-completion clash between arm64/arm_tf.c and arm64/armv8. Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-30intel/quark: Use common romstage entryKyösti Mälkki
Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30intel/quark: Select NO_SMMKyösti Mälkki
SoC was unintentionally flagged with SMM_TSEG when default values were assigned. Change-Id: I83202316f41ead66c7f69cad68dafaeccd09df66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-30intel/quark: Remove extra steps on entry to romstageKyösti Mälkki
Change-Id: I9297d5b4f7c8ed703fb8772739531cdd7d5ca5f0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-29intel/fsp_broadwell_de: Move and rename smm_lock()Kyösti Mälkki
There will be inlined smm_lock() that would conflict with this special case. Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34874 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29intel/fsp_broadwell_de: Use smm_subregion()Kyösti Mälkki
Tested on OCP/Wedge100s: No error is visible in console output, still boots to OS. Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34745 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-29soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functionsPatrick Rudolph
Implement sa_get_tseg_base and sa_get_tseg_size. Used by Intel TXT and the new SMM API. Tested on OCP/Wedge100S. Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-28intel/broadwell: Use smm_subregion()Kyösti Mälkki
Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/haswell,broadwell: Rename EMRR to PRMRRKyösti Mälkki
The MSRs were already named as PRMRR in broadwell, just mismatching with the rest of the code. All later devices use the names PRMRR and UNCORE_PRMRR for these MSRs. Reflect the name change in structures and local variables. Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/braswell: Use smm_subregion()Kyösti Mälkki
Change-Id: I4af661f68c158cbed591fe017d4bc25239bddd37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34758 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28intel/fsp_baytrail: Use smm_subregion()Kyösti Mälkki
Change-Id: I4e9de9c7f5decd784d881e5a733e995522be5226 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28google/rambi,intel/baytrail: Simplified romstage flowKyösti Mälkki
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28soc/intel: Move fill_postcar_frame to memmap.cKyösti Mälkki
Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28soc/intel/cnl: Add CML IGD IDsMeera Ravindranath
BUG=b:139798422 TEST=Build and boot CMLRVP. Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-08-28soc/intel/common/block: Provide mmc.c for setting dll registersKane Chen
Currently, we don't have UPDs to set emmc settings per mainboard on CML. This code change is to create mmc.c to provide interface to override dll settings per mainboard. Notice: set_mmc_dll function will override the dll values in FSP. BUG=b:131401116 BRANCH=none TEST=Boot to OS and confirm the dll values have been overridden. Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383 Signed-off-by: Kane Chen <kane.chen@intel.com> Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-27intel/baytrail: Use smm_subregion()Kyösti Mälkki
Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34739 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27intel/baytrail: Reorganize romstage.cKyösti Mälkki
Done just for future review convenience. Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34910 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27soc/intel/fsp_broadwell_de: Add ACPI HPET tableJohnny Lin
Tested on Mono Lake TEST=Note the kernel log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35027 Reviewed-by: Johnny Lin Reviewed-by: Andrey Petrov <anpetrov@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-27soc/intel/{apl,cnl,dnv,icl,skl} : Use common cpu/intel/car/romstage.c codeSubrata Banik
This patch includes common romstage code to setup the console and load postcar. Fix booting regression issue on all latest IA-SOC introduced by CB:34893 Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-26intel/car: Use common TS_START_ROMSTAGEKyösti Mälkki
This timestamp also got unintentionally removed from some boards as they were transformed to use common romstage entry. Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26lib/bootblock: Add simplified entry with basetimeKyösti Mälkki
This allows for minor optimization as num_timestamps becomes a constant zero for a function with local scope. The loop with calls to timestamp_add() gets removed from bootblock. Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 12:29:48 +0000