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path: root/src/soc
AgeCommit message (Expand)Author
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
2014-11-12Include IPQ8064 SBLs code in the coreboot bootblockVadim Bendebury
2014-11-12tegra124: enable JTAG in Security ModeJimmy Zhang
2014-11-12tegra124: Program PWM1 to drive panel backlightAndrew Chew
2014-11-12tegra124: Add pwm_controller registersAndrew Chew
2014-11-12tegra124: Fix PWM pinmux functionsAndrew Chew
2014-11-12tegra124: Add PWM base addressAndrew Chew
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-09Provide ability to integrate with QComm SBLsVadim Bendebury
2014-11-09arm: Thumb ALL the things!Julius Werner
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22tegra/nyan*: sdram updatesTom Warren
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
2014-10-22broadwell: Update microcodeDuncan Laurie
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
2014-10-22broadwell: add new intel SOCDuncan Laurie
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
2014-10-16uarts: 32/64 cleanupRonald G. Minnich
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
2014-10-14intel/fsp_baytrail: Clear the GNVS area prior to fillingScott Radcliffe
2014-10-09intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route"Kayalvizhi Dhandapani
2014-10-09intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module addedKayalvizhi Dhandapani
2014-10-09intel/fsp_baytrail: Fix SMM/SMIKayalvizhi Dhandapani
2014-10-01baytrail: update C0 microcodeShawn Nematbakhsh
2014-09-29intel/fsp_baytrail: Add S3 suspend/resume SupportMohan D'Costa
2014-09-25soc/qualcomm: Add generic support skeleton for ipq806xFurquan Shaikh
2014-09-24baytrail: add 80c microcode for C0 partsAaron Durbin
2014-09-22tegra124/nyan: memory and display updatesAndrew Bresticker
2014-09-22arm: Move libgcc assembly macros to arch/asm.hJulius Werner
2014-09-22Add check_member macro to allow clean and easy struct offset checkingJulius Werner
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