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2017-12-23soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
BUG=b:70628116 Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22956 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-23soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides a new Kconfig option that can be selected by SoCs using these new bit definitions of SPI_CS_CONTROL. Common code takes care of setting the right value for polarity and state field depending upon the version selected by SoC. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-23soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in ↵Subrata Banik
weak function This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()Richard Spiegel
Issue first reported at commit 1587dc8a2b, the call of functions setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev() to soc_init(). The function setup_uma_memory() no longer exists, its functionality transfered to agesawrapper_amdinitpost. Move setup_bsp_ramtop() as required. BUG=b:62240756 TEST=Build and boot kahlee. Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-22soc/intel: Treat time-out as failure in HECILijian Zhao
If HECI gets times out when waiting for read slots, there's no need to read back reply message to decide if the HECI recieve successed or not. Otherwise, system will stuck after global reset required. BUG=b:707290799 TEST=Boot up meowth board without battery, and confirm hard reset got trigged after heci time out. Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22amd/stoneyridge: Increase pre-cbmem console sizeMarshall Dawson
The existing stoneyridge pre-cbmem console log contains about 250 bytes of unused space. Increase this amount to accomodate any additional debug messages. BUG=b:64980233 TEST=Build and boot Kahlee, inspect console log with "cbmem -c" Change-Id: Ia307795e91d81ff9b2be027916081f6824f90bad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22ic2/designware: Move Intel i2c logic to shared driverChris Ching
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/amd/stoneyridge: select RTCMarc Jones
Stoneyridge has an RTC. Elog requires it for timestamps. BUG=b:65485690 TEST=Build Kahlee with Elog. Check mosys eventlog list for timestamps. Change-Id: I4d820fbe11043e7e3153d67159f52274d5f14bae Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-22soc/intel/skylake: Make use of common SMM code for SKLSubrata Banik
This patch ensures skylake soc is using common SMM code from intel common block. TEST=Build and boot soraka/eve Change-Id: I8163dc7e18bb417e8c18a12628988959c128b3df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/22826 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-22soc/intel/cannonlake: Add SoC API to make use SMM common codeSubrata Banik
Add SoC API to detect any illegal access to write into the BIOS located in the FWH. Change-Id: If526cbae9afee47fa272bdf74e04416aff100e88 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22soc/intel/common: Add missing SoC common function into SMM librarySubrata Banik
Modify SMM common code in order to accommodate SKL, CNL, APL, GLK SOC code. Change-Id: Ie9f90df3336c1278b73284815b5197400512c1d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDSSubrata Banik
TEST=CNL_RVP is able to power on after reconnecting power supply. Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22840 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.cSubrata Banik
Original commit hash aeb2d64c85ca2c3a77f50d57e3a92f6fc0a5c2d3 (soc/intel/skylake: Enable power button SMI when jumping to payload) Change-Id: Ia4fe2694006baf24ed475c85aaffa6a0d2a6031d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22868 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDSSubrata Banik
TEST=KBL_RVP is able to power on after reconnecting power supply. Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-21soc/intel/common: Add API to restore power failure into PMC common codeSubrata Banik
PMC config register need to program to define which state system should be after reapplied power from G3 state. 0 = System will return to S0 state 1 = System will return to S5 state 2 = System will return to previous state before failure Refer to EDS for detailed programming sequence. Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22838 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-20soc/intel/apollolake: Add SMI and SCI support for ESPIShaunak Saha
This patch adds the SMI bits for SMI_EN, SMI_STS and GPE register in pm.h. The southbridge handler for espi smi is also added. In gpe.h we add GPE0A_ESPI_SCI_STS which is bit 20 in GPE register and enables the setting of the ESPI_SCI STS bit to generate a wake event and/or an SCI/SMI. TEST= Boot to OS. Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22758 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20soc/intel/denverton_ns: Add Denverton-AD system agent idLew, Chee Soon
This is to add support for Denverton-AD soc. Change-Id: I539abedd65bcbdb97b64f58d0b2273ff8eb67420 Signed-off-by: Lew, Chee Soon <chee.soon.lew@intel.com> Reviewed-on: https://review.coreboot.org/22605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20soc/intel/cannonlake: Tell FSPM UART port numberLijian Zhao
Cannonlake FSP will send debug message on selected UART port, use same coreboot UART debug port to FSP. TEST=Boot up with board have UART port 0 and can see the print of FSP Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Add BootDone commandMarshall Dawson
After the PSP receives the MboxBiosCmdBootDone, it will no longer honor any command where the command-response buffer exists outside of SMM memory. Add the command and automatically execute it before booting the payload. BUG=b:69971683 TEST=Boot Kahlee and observe console log Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Convert structure init to C99Marshall Dawson
Use C99 designated initializers for the psp_notify_dram() buffer structure. Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Assume PSP command register already set upMarshall Dawson
Remove the frequent setting/restoring of the PSP's bus-mastering and memory decoding settings. It is up to the caller to ensure it is already set properly. Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/stoneyridge: Force PSP command reg settings in bootblockMarshall Dawson
A subsequent patch to the PSP library will rely on the device already having its PCI command register set to allow memory decoding and mastering enabled. Program the command register ahead of loading the SMU FW1 blob in bootblock. When the device has not been set up (e.g. when SMU FW is not selectable), AGESA sets up the device. As a result, a similar change is not required before sending the DRAM ready command. Change-Id: Id586106751286c4767b5c16ed7e1604523635492 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19soc/amd/common/block/pci: Fix validation of pointerRichard Spiegel
Procedure write_pci_int_table() does not validates intr_data_ptr. It must be validated together with picr_data_ptr and idx_name. BUG=b:69868534 TEST=Build fake kahlee with intr_data_ptr not initialized, boot and see error message. Than build correct kahlee and verify that error message is gone. Change-Id: I5ee9a362600dbd6325254d7431172501181b52b0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-19soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused valueRichard Spiegel
In function load_smu_fw1(), variable base receives one value and is immediately overwritten. Remove the first line, as it's useless. This fixes CID 1383612 BUG=b:70620140 TEST=Build kahlee and boot. Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18amd/stoneyridge: Skip VGA initialization on S3 resumeMarshall Dawson
Sync with the other AMD implementations. Change-Id: I222cc7fcf5e58f451cee9621a1b876346226af09 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd/common: Factor out InitPost printed results to functionMarshall Dawson
Make a static function that can report the AmdInitPost() results. This makes it easier to keep lines within 80 columns. Clean up surrounding source. BUG=b:62240746 TEST=Build and boot Kahlee Change-Id: I6d288e76e7510528659436e61fdfa1d5db01f06c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-18soc/amd: Move stoneyridge features out of agesawrapperMarshall Dawson
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should it make any assumptions about the capabilities of a particular device. Move these into stoneyridge northbridge and southbridge files. BUG=b:70670425 TEST=Build and run Kahlee Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd/common: Remove #ifndef/#endif from AGESA wrapperMarshall Dawson
There isn't a good reason to keep the checks for __PRE_RAM__. The global variables are not used outside of ramstage and the linker removes them cleanly in other stages. BUG=b:70671590 TEST=Build and boot Kahlee Change-Id: I7a35141f212f340c157d57fde8daf93c0c383af8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-18soc/amd/common: Make AGESA event log parser staticMarshall Dawson
The function agesawrapper_readeventlog() is not used outside of the wrapper. Relocate it within the file and make it static. Change-Id: Ia7fefb4eadbace0cc2fb0f519a1acb7906baaf12 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-18soc/amd/common: Clean up AGESA event log functionMarshall Dawson
Clean up the source for agesawrapper_amdreadeventlog: * shorten the name to help keep lines within 80 columns * convert initializers to C99 * break the call from the callers' if() statements * streamline the printk formatting BUG=b:70671442 TEST=Build and run Kahlee, check console log Change-Id: I402c75e4d65a592b9d1557c5852df03e48e206b9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-17drivers/mrc_cache: move mrc_cache support to driversAaron Durbin
There's nothing intel-specific about the current mrc_cache support. It's logic manages saving non-volatile areas into the boot media. Therefore, expose it to the rest of the system for any and all to use. BUG=b:69614064 Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-17soc/intel/apollolake: move default y options to CPU_SPECIFIC_OPTIONSAaron Durbin
A non-user configurable option that defaults to y should just be auto-selected instead of instantiating an instance of an option. BUG=b:69614064 Change-Id: I55cf28eaf0233182d4fa488cf4b31e8ad379b6c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-17soc/intel/broadwell: remove CACHE_MRC_SETTINGS optionAaron Durbin
The CPU_SPECIFIC_OPTIONS already auto-selects the option. There's no point in having a selectable option that is already selected. There's already an option to select it within intel/common. BUG=b:69614064 Change-Id: I0c7ce7d3f344668587a75ec683343559a4caea99 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-17soc/intel/fsp_baytrail: remove nvm headers and codeAaron Durbin
This code is not used at all any longer. Remove it. BUG=b:69614064 Change-Id: I362280f876a335c0cc1c5691b86f5b27e3b5e2c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-16soc/intel/common: remove nvm headers and c fileAaron Durbin
There's no sense in having the nvm abstraction in its own files. Put that support directly into mrc_cache.c. BUG=b:69614064 Change-Id: I0f1a801c6e1a8c35f70faf9e4318bdc45955047a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-16soc/intel/broadwell: implement spi_flash_ctrlr_protect_region()Aaron Durbin
Implement the spi controller flash_protect() callback. No need to have a global spi_flash_protect() once implemented. BUG=b:69614064 Change-Id: I83f4310d8f78ba64727ba75eb75708d0cbaa7d53 Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-16soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()Aaron Durbin
In the fast spi support implement the callback for flash_protect(). This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT Kconfig option as well spi_flash_get_fpr_info() and separate spi_flash.[ch]. BUG=b:69614064 Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-15soc/intel/common/nvm: utilize spi_flash_ctrlr_protect_region()Aaron Durbin
Now that there is spi flash controller flash protection use that API so the spi_flash_protect() API can be sunsetted since it was isolated within the Intel code base. BUG=b:69614064 Change-Id: I3908d0e3105b0ef9a0fbf4fc9426ac1be067f648 Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-15soc/intel/apollolake: Remove duplicate selectsMarshall Dawson
Remove Kconfig selected symbols that are duplicates in the same file. Change-Id: I21a3814131f0c8e08732e826dd1bcbb677cbe0aa Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22852 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-15soc/amd/common: Update agesawrapper_call.hRichard Spiegel
Solve issues related to agesawrapper_call.h that came up at review 75dd50e233 (review 19724). This includes a hard coded table size and 2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER(). Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with the actual content of the macro. BUG=b:62240989 TEST=Build kahlee with no errors, boot recording serial output and compare to serial output from a build without these changes. Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14soc/intel/skylake: Add integrated LAN config parametersDuncan Laurie
Add parameters to configure the integrated LAN via FSP. Since this takes over a PCI CLKREQ# pin it needs to know which pin it should use, and there are additional parameters for LTR and a "K1 power save" feature. This was tested on a KBL-R board with integrated LAN, verifying that the device is functional under Linux with the e1000e driver. Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22856 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14soc/intel/apollolake: add _RMV attributes to eMMC device ACPIPatrick Georgi
Required so Windows knows if the storage is removable or not. Change-Id: I0822d767ada872d55357ff229e47e08fbe778a36 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/22830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14soc/intel/common/block/i2c: fix orphaned Kconfig optionsAaron Durbin
The SOC_INTEL_COMMON_LPSS_I2C option is no longer used. Likewise, the SOC_INTEL_COMMON_LPSS_I2C_DEBUG option which is dependent on SOC_INTEL_COMMON_LPSS_I2C is by definition not used either. Therefore, remove SOC_INTEL_COMMON_LPSS_I2C and change the name/dependency for SOC_INTEL_COMMON_LPSS_I2C_DEBUG to SOC_INTEL_COMMON_BLOCK_I2C_DEBUG. BUG=b:70232394 Change-Id: Icd77f028b77d8f642690a50be4ac2c50d9ef511a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22874 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-12-14src/soc/intel/apollolake: include helpers.h in chip.hPratik Prajapati
include helpers.h in chip.h so that devicetree can use macros from helpers.h Change-Id: Idfdee637a9b66a30be31b9ed113e1a44e4032f34 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/22774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-14soc/intel/cannonlake: Fix UART2 serial log broken issueSubrata Banik
Cannonlake rvp serial log has been regressed with commit I7eea910e065242689e87adac41281131674b39af(soc/intel/cannonlake: Clean up UART code) because of common UART code is unable to link all __weak function implementation from SoC uart.c due to existing macro #define __SIMPLE_DEVICE__. Hence UART2 PCI device resource programming is different than what it's been programmed before. This patch ensures UART2 PCI device resource enumeration is working and we are getting serial log as expected. Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22862 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14soc/amd/stoneyridge: Remove "\t" from name tableRichard Spiegel
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array irq_association[], and change the print string in soc/amd/common/amd_pci_util.c that use the names from "%s" to "%-20s". This sets a fixed field of 20 characters for the string name, allowing for variable length to the names (up to 20 characters), thus saving memory space used by the strings. BUG=b:70344551 TEST=Build and boot, record output of irq routing and verify alignment. Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-13src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik
Add _PRW so that wake on WLAN feature works. TEST=Boot to OS and check if WLAN device wakes host. Change-Id: Id6689754d1c4100615e4e4ae5a7f9846f4bf785f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-12-13vc/amd/pi/0067F00: add option to add AGESA binary PI as stageAaron Durbin
Stage addition to CBFS allows relocation to happen on the fly. Take advantage of that by adding AGESA binary PI as a stage file so that each instance will be relocated properly within CBFS. Without this patch Chrome OS having multiple CBFS instances just redirects the AGESA calls back into RO which is inappropriate. BUG=b:65442265,b:68141063 TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and noted each instance in Chrome OS build was relocated. Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-13soc/intel/skylake: make tcc_offset take effectmarxwang
Currently, "tcc_offset" defined in devicetree is overwritten by Intel FSP-S UPD "TccActivationOffset". This patch will make "TccActivationOffset" refer to "tcc_offset". TEST=check if MSR (0x1a2[29:24]) value is updated with "tcc_offset" by iotools (rdmsr 0 0x1a2). Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/22818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 07:29:35 +0000