| Age | Commit message (Expand) | Author |
|---|
| 2020-09-08 | soc/intel/broadwell: Drop `gpu_panel_port_select` | Angel Pons |
| 2020-09-08 | soc/intel/tigerlake: Add SMRR Locking support | Tim Wawrzynczak |
| 2020-09-08 | soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP | Tim Wawrzynczak |
| 2020-09-08 | soc/mediatek/mt8192: Add SPI flash controller DMA read function | CK Hu |
| 2020-09-06 | soc/intel/apl: Add panel power and backlight configuration | Nico Huber |
| 2020-09-06 | soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default | Michael Niewöhner |
| 2020-09-05 | soc/intel/alderlake/bootblock: Do initial SoC commit till bootblock | Subrata Banik |
| 2020-09-04 | soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO... | Elyes HAOUAS |
| 2020-09-04 | soc/intel/cnl: Enable HECI3 depending on devicetree | Felix Singer |
| 2020-09-04 | soc/intel/tigerlake: Remove unused PID_SDX macro | Subrata Banik |
| 2020-09-03 | soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment. | Jason Glenesk |
| 2020-09-03 | soc/amd/picasso: Set max_speed_mts and configured_speed_mts | Rob Barnes |
| 2020-09-03 | soc/intel/cnl: Allow using the remaining Comet Lake FSPs | Felix Singer |
| 2020-09-03 | 3rdparty/fsp: Update submodule pointer to current master | Felix Singer |
| 2020-09-03 | soc/intel/cnl: Add new Kconfig option which matches its FSPs name | Felix Singer |
| 2020-09-03 | soc/amd/picasso: Only build PSP bootloader & verstage into RO | Martin Roth |
| 2020-09-03 | soc/amd/picasso: Add config for PSP verstage signing token | Martin Roth |
| 2020-09-03 | soc/amd/picasso: Allow use of pre-built PSP verstage | Martin Roth |
| 2020-09-03 | soc/amd/picasso: Move DRAM end to after transfer buffer | Josie Nordrum |
| 2020-09-02 | soc/intel/tigerlake: Add mainboard hook for overriding SoC config | Jes Klinke |
| 2020-09-02 | src: Drop redundant 'select BOOTBLOCK_CONSOLE' | Elyes HAOUAS |
| 2020-09-02 | soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE' | Elyes HAOUAS |
| 2020-09-02 | {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a) | Elyes HAOUAS |
| 2020-09-01 | {include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent | Subrata Banik |
| 2020-08-31 | soc/intel/elkhartlake/romstage: Do initial SoC commit till romstage | Tan, Lean Sheng |
| 2020-08-31 | soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblock | Tan, Lean Sheng |
| 2020-08-31 | soc/amd/picasso/southbridge: make GPP clock outputs configurable | Felix Held |
| 2020-08-31 | soc/amd/picasso/southbridge.h: rename GPP clock setting offsets | Felix Held |
| 2020-08-31 | soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macros | Felix Held |
| 2020-08-31 | soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitions | Felix Held |
| 2020-08-31 | {intel/gma,include/device}: Delete unused 'drm_dp_helper.h' file | Elyes HAOUAS |
| 2020-08-29 | PCI IDs: Add PCI ID for CML DPTF/DTT PCI device | Edward O'Callaghan |
| 2020-08-28 | amd/picasso/psp_verstage: add vboot rsa function | Kangheui Won |
| 2020-08-28 | soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled | Matt Papageorge |
| 2020-08-28 | vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc | Jonathan Zhang |
| 2020-08-28 | soc/intel/tigerlake: add ddr4-spd-empty.hex | Aaron Durbin |
| 2020-08-28 | mb/google/zork: Switch zork to use spd_tools | Rob Barnes |
| 2020-08-28 | util: Add memory parts needed by zork boards | Rob Barnes |
| 2020-08-28 | util/gen_spd: translate DeviceBusWidth to die bus width | Nick Vaccaro |
| 2020-08-28 | soc/mediatek/mt8192: Use SPI-NOR as flash controller | CK Hu |
| 2020-08-28 | util: rename lp4x spds to include "lp4x-" in name | Nick Vaccaro |
| 2020-08-28 | util: volteer/dedede: move generic SPDs to common location | Nick Vaccaro |
| 2020-08-27 | symbols: Change implementation details of DECLARE_OPTIONAL_REGION() | Julius Werner |
| 2020-08-27 | soc/intel/common: Include Elkhart Lake SA IDs | Tan, Lean Sheng |
| 2020-08-27 | soc/intel/common: Add Elkhart Lake B0 CPU ID | Tan, Lean Sheng |
| 2020-08-26 | soc/mediatek: Include addressmap.h in gpio_common.h | CK Hu |
| 2020-08-26 | soc/intel/tigerlake: Rename pch_init() code | Alexey Buyanov |
| 2020-08-25 | util: Add spd_tools to generate DDR4 SPDs for TGL boards | Nick Vaccaro |
| 2020-08-25 | soc/amd/picasso: If psp_verstage is in RO, don't reset on error | Martin Roth |
| 2020-08-25 | soc/mediatek/mt8192: Add dramc param struct | Huayang Duan |
