summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2014-05-15baytrail: Add SOC thermal settingsDuncan Laurie
Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-15baytrail: Enable PCIe common clock and ASPMDuncan Laurie
Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: enable graphics turboAaron Durbin
Though the limited documentation indicates the default is 0 for the gfx_turbo_disable bit, in practice that isn't true. Knock down the gfs_turbo_disable bit to enable graphics turbo mode. BUG=chrome-os-partner:25044 BRANCH=baytrail TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG. Noted that bit 7 was set to 0. Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5050 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPEDAaron Durbin
On baytrail, it appears that the turbo disable setting is actually building-block scoped. One can see this on quad core parts where if enable_turbo() is called only on the BSP then only cpus 0 and 1 have turbo enabled. Fix this by calling enable_turbo() on all non-bsp cpus. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and booted rambi. All cpus have bit 38 set to 0 in msr 0x1a0. Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182406 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: Add ACPI Device for XHCIDuncan Laurie
This will allow USB devices to wake the system (if 5V is not turned off) and the controller to enter D3 at runtime. (if autosuspend is enabled) BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on baytrail 1) with modified EC to leave 5V on in S3 ensure that waking from suspend with USB keyboard works. 2) with laptop-mode-tools usb autosuepend config updated see that device enters D3 at runtime when no external devices attached. Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182536 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: nvm: use proper types for checking eraseAaron Durbin
The current byte value was being converted to an int when checking against literal 0xff. As the type of the current pointer was char (signed) it was sign extending the value leading to 0xffffffff != 0xff. Fix this by using an unsigned type and using a constant type for expected erase value. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmwareupdate. Noted that MRC cache doesn't think the erased region isn't erased. Change-Id: If95425fe26da050acb25f52bea060e288ad3633c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: mrc_cache: check region erased before erasingAaron Durbin
On a firmware update the MRC cache is destroyed. On the subsequent boot the MRC region was attempted to be erased even if it was already erased. This led to spi part taking longer than it should have for an unnecessary erase operation. Therefore, check that the region is erased before issuing the erease command. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmeareupdate. Noted no error messages in this path. Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-13baytrail: add C0 microcode updateAaron Durbin
Include C0 microcode drop. BUG=None BRANCH=rambi,squawks TEST=Built. Booted B3 part. Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182080 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5041 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: reboot with EC in S0 with no MRC cache and EC in RWAaron Durbin
This improves boot time in 2 ways for a firmware upgrade: 1. Normally MRC would detect the S0 state without an MRC cache even though it's told to the S5 path. When it observes this state a cold reset occurs. The cold reset stays in S5 for at least 4 seconds which is time observed by the end user. 2. As the EC was running RW code before the reset after firmware upgrade it will still be running the older RW code. Vboot will then reboot the EC and the whole system to put the EC into RO mode so it can handle the RW update. The issues are mitigated by detecting the system is in S0 with no MRC cache and the EC isn't in RO mode. Therefore we can do the reboot without waiting the 4 secs and the EC is running RO so the 2nd reboot is not necessary. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Booted. Updated firmware while in OS. Rebooted. Noted the EC reboot before MRC execution. Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182061 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: dptf: Add disable trip point methodsDuncan Laurie
Added a method in each temp sensor to disable the aux trip points and then a wrapper function to call this method for each enabled temperature sensor. The event handler function is changed to not use a switch statement so it does not need to be serialized. This was causing issues with nested locking between the global lock and the EC PATM mutex. Some unused code in temp sensors that was added earlier is removed and instead a critical threshold is specified in _CRT. The top level DPTF device _OSC method is expanded to check for the passive policy UUID and initialize thermal devices. This is done for both enable and disable steps to ensure that the EC thermal thresholds are reset in both cases. Additionally the priority based _TRT is specified with TRTR=1. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and start esif_uf application. Observe that temperature thresholds are set properly when running 'appstart Dptf' and that they are disabled after running 'appstop Dptf' Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182024 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5037 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: Updates for DPTF ACPI frameworkDuncan Laurie
- Remove some unused functions from CPU participant that were confusing the userland component since the CPU does not have an ACPI managed sensor. - Guard the charger participant with an ifdef so it can be left out if not supported. - Use the EC methods for setting auxiliary trip points and for handling the event when those trip points are crossed. - Add _NTT _DTI _SCP methods for thermal sensors. I'm not clear if these are required or not but they seem to be expected by the other DPTF framework components. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and load ESIF framework Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5028 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: don't SMI on tco timer firingAaron Durbin
The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181985 Reviewed-on: http://review.coreboot.org/5035 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: clear the pmc wake status registersAaron Durbin
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: log reset, power, and wake events in elogAaron Durbin
When CONFIG_ELOG is selected the reset, power, and wake events are logged in the eventlog. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Various resets and wake sources. Interrogated eventlog to ensure results are expected. Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181983 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: snapshot power state in romstageAaron Durbin
The memory reference code doesn't maintain some of the registers which contain valuable information in order to log correct reset and wake events in the eventlog. Therefore snapshot the registers which matter in this area so that they can be consumed by ramstage. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Did various resets/wakes with logging patch which consumes this structure. Eventlog can pick up reset events and power failures. Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181982 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: add cpuid for C0Aaron Durbin
The C0 part uses a new cpuid. BUG=None BRANCH=squawks,rambi TEST=None. Change-Id: Iddf1bc4d6f7bbec3ca92bff8edf613e00a4b4286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181980 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12baytrail: align with intel recommendationsAaron Durbin
The BISOC.EXIT_SELF_REFRESH_LATENCY field should not be updated from the default. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180730 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5025 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: add way to load reference code from vboot areaAaron Durbin
When employing vboot firmware verification the reference code loading should load from the verified firmware section. Add this ability. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted rambi. Noted firmware being loaded from rw verified area. Also noted S3 resume loading from cached area. Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180026 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5023 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12baytrail: Expose IOSF as ACPI objectDuncan Laurie
The kernel iosf driver uses HID INT33BD to probe and be provided the 12 bytes in PCI for access. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, load iosf_mbi driver and verify that it gets address 0xe00000d0 Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180098 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: Put devices in ACPI mode after setupDuncan Laurie
Make sure reg_script is executed before the device is put into ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi from eMMC in ACPI mode Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5017 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: Add header include wrapper and offset defineDuncan Laurie
Since this file will get added to payloads it is useful if it exports what offset in NVS it lives. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I52860980c91dfe2525628e142b34ca192e69b258 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179848 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5014 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-10baytrail: cache reference code for S3 resumeAaron Durbin
In order to use the same reference code on S3 resume that was booted the program needs to be cached. Piggy back on the ramstage cache to save the loaded reference code program. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Noted locations of reference code caching and load addresses in console. Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179777 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5013 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: allow ramstage_cache_location() usage in ramstageAaron Durbin
To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: note S3 resume status earlierAaron Durbin
Certain code paths want to know if S3 resume is happening. However, the current baytrail code doesn't note S3 resume early enough. Therefore, mark S3 resume just after pattr setup. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179774 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5010 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: utilize reg_script_run_on_dev()Aaron Durbin
The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin@chromium.og> Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: initialize perf/power registersAaron Durbin
According to the reference code all these registers need to be set to their best known values. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. No idea about observable impact yet. Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179749 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5008 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: add more iosf access functionsAaron Durbin
There's a slew of ports required to initialize baytrail's perf and power values. Therefore, add the necessary functionality in the iosf module as well as the reg_script library. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179748 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5007 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: remove verbosity in iosfAaron Durbin
The iosf access functions already use some common code, however there is a duplication for setting up the proper control register for port and opcode. Introduce macros to remove this verbosity. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179747 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5006 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: Add support for LPSS and SCC devices in ACPI modeDuncan Laurie
This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179481 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5004 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09baytrail: Basic DPTF frameworkDuncan Laurie
This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179459 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09baytrail: Enable panel and set timingsDuncan Laurie
These need to be set before the kernel will work without running the VBIOS option rom. Also necessary is setting the PP_CONTROL register with the EDP_FORCE_VDD bit. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179364 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5000 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09baytrail: allow SD card controller capabilities overridesAaron Durbin
The SD card controller can have the capabilities it supports to be overridden. Add two optional fields to the chip structure to allow the mainboard to override the SD card controller capabilities. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. Noted capabilities override console output. Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179414 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4997 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09baytrail: fix nvs offsetsAaron Durbin
The VDAT data was off by 2 bytes when reading it from the kernel. The reason is that the header did not line up correctly with actual ACPI code. BUG=chrome-os-partner:24440 BRANCH=None TEST=crossystem devsw_cur now returns either 0 or 1 depending on state. Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a Signed-off-by: Aaron durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179372 Reviewed-on: http://review.coreboot.org/4996 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09baytrail: lpe audio device needs memory for its firmwareAaron Durbin
The LPE audio device needs 1MiB of memory for its firmware. It also has a requirement that the memory needs to be on a 512MiB boundary. Just take 1MiB @ 512MiB for the LPE device. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and analyzed console logs for resources. Also interrogated registres within the kernel. Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b Reviewed-on: https://chromium-review.googlesource.com/179192 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4994 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: gpio: Make GPIO inputs MMIO by defaultShawn Nematbakhsh
The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the default input GPIO type MMIO. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat /sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic jack status. BRANCH=None Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179169 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4992 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: enable lpe resources assigned to deviceAaron Durbin
The enable_resources callback was accidentally populated with NULL. Make that callback be the generic pci_dev_enable_resources. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Change-Id: I670b51bd9aff6764e9b549287a737b662572cdc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178960 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4989 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: Fix _CRS to build with new IASLDuncan Laurie
The new IASL is complaining about the PCI memory region not having consistent base/end/length values because they are placeholder that are fixed up in the method before returning. Put in some more valid placeholder values to make it happy. BUG=chromium:311294 BRANCH=none TEST=build and boot with IASL 20130117 on rambi Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178864 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4988 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: add lpe codec clock configurationAaron Durbin
Add device tree option to determine if the LPE audio codec has a platform clock signal connected to it from the SoC. If a frequency is selected the platform clock number is used to enable the clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted rambi with 25MHz option. Probed pin to audio codec. Noted 25MHz clock. Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178780 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4986 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: Add ACPI code to describe GPIO controllerDuncan Laurie
There are 3 banks of GPIOs that need to be described with specific _UID and memory/interrupt values. BUG=chrome-os-partner:24314 BRANCH=none TEST=build and boot on rambi, check for probed driver: gpiochip_find_base: found new base at 154 gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00 gpiochip_find_base: found new base at 126 gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01 gpiochip_find_base: found new base at 82 gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02 fed0c000-fed0cfff : INT33FC:00 fed0c000-fed0cfff : INT33FC:00 fed0d000-fed0dfff : INT33FC:01 fed0d000-fed0dfff : INT33FC:01 fed0e000-fed0efff : INT33FC:02 fed0e000-fed0efff : INT33FC:02 Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178601 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4985 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: Update to microcode 31E and fix C-state tableDuncan Laurie
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi, check that C1/C2/C3 are all used now Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178461 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4984 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07baytrail: minor stylePatrick Georgi
use IS_ENABLED() over #if brackets Change-Id: I101f99971c0f7b5311ef19cc9832713ab0696935 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5692 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07baytrail: romstage: Add config option to enable RMTShawn Nematbakhsh
Add config option to enable RMT in the MRC. BUG=chrome-os-partner:21807 TEST=Manual. Build w/ "USE=rmt", verify RMT print seen on FW console. Build w/o USE flag, verify no RMT print. BRANCH=None. CQ-DEPEND=CL:*148655 Change-Id: Ibd3da87317a3359e797d9b43bc437e7227a85048 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4982 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: pcie: Root port initializationAaron Durbin
Add PCIe driver to initialize root ports. BUG=chrome-os-partner:24111 TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to detect networks. BRANCH=None. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12 Reviewed-on: https://chromium-review.googlesource.com/177652 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: gpio: Fix NCORE gpio-to-pad LUTShawn Nematbakhsh
NCORE pad addresses were wildly wrong due to documentation bugs. BUG=chrome-os-partner:24179 TEST=Manual on Rambi. Verify display isn't always on. Verify brightness control now works in Chrome OS. BRANCH=None. Change-Id: I464436a58baa4957329c11231c5a866dafd97ce8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177597 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4980 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: enable caching and prefetching in spi controllerAaron Durbin
The default mode of the SPI controller has prefetching disabled. That obviously has a performance impact. Enable both caching and prefetching to make booting faster. This has a significant impact on streaming data out of SPI. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted rambi. Payload loading step went from ~285ms to ~54ms. Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177220 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: fix direct irq pad configurationAaron Durbin
When a pad is configured for direct IRQ it needs to be in non-legacy. Additionally, the signal is passed directly to the APIC by setting the LEVEL and TPE bits in the pad config register. The APIC can then be configured for level, edge, and rising/falling. BUG=chrome-os-partner:24037 BUG=chrome-os-partner:22863 BRANCH=None TEST=Built and booted with this config. Trackpad is firing interrupts more than it should, but it appears to be a trackpad firmware and/or configuration issue. Change-Id: I00042b2ddba67d6bf23f0e7468d0719196e6f865 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176793 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4975 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: ensure init_chromeos() is called in romstageAaron Durbin
The TPM needs to have the TPM_Startup command sent to it on all boot paths. The call init_chromeos() in romstage_common() fulfills this requirement. BUG=chrome-os-partner:24057 BRANCH=None TEST=Built and booted. Was able to suspend to ram multiple times in a row. Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176803 Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-07baytrail: don't allow PCIE wake upsAaron Durbin
The PCIe subsystem was constantly waking up boards from S3 and S5. Completely disable PCIe wake ups. It can be made mainboard-configurable later if needed. BUG=chrome-os-partner:24004 BRANCH=None TEST=Both S3 and EC RW->RW update (trip through S5) don't cause wakeups. Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176791 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4972 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: gpio: Make pad input/output state mutually exclusiveShawn Nematbakhsh
Previously pads were being configured as both input and output simultaneously due to the config bits being active low. Create new defines that only enable either input or output, and use them in our GPIO configs. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Verify system boots and peripherals still function. BRANCH=None. Change-Id: If386682a3d810864b7b9f5d2aecdb2e6cfceea86 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4971 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: first pass at lpss device initializationAaron Durbin
This commit does the common parts for all LPSS devices that are enabled: enable snoop in IOSF and enable power management. Additionally, the i2c devices are taken out of reset. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted with modified kernel-next. I2C bus devices show up and I see 0x10 on one of the buses. Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176424 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4969 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 20:24:40 +0000