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2016-05-09soc/intel/apollolake: Select no stage caching for resumeFurquan Shaikh
Select NO_STAGE_CACHE so that ramstage is not cached for resume. Change-Id: I9ca71686e0f617bb24713ec9ba07b5255c218f66 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09soc/apollolake/pmutil: Get PMC base address dynamicallyAlexandru Gagniuc
Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09soc/intel/quark: Identify the console UARTLee Leahy
Pass the UART identifier to CorebootPayloadPkg Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09rockchip/rk3399: protect the DRAM address for atfCaesar Wang
We need ensure the bl31 base is greater than 4KB since there's the shared mem for coreboot. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to kernel with atf patch Change-Id: I44cf436b3072f03b93da4a19227dcc540d7513db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a462f604c284c84bd8c5a0420e75eeae5035b382 Original-Change-Id: I55ec134762bb6bcbc91937ad5763617d7488490b Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342334 Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: move vop driver from rk3288 to rockchip commonShunqian Zheng
The rk3288 and rk3399 can use a common driver even that there are some different registers. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from veyron_jerry and check display Change-Id: I510f68ba00308e47608d6e9921154a5c66ad8858 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d857a7aa68d831a5007210255b121fed7a9e8de Original-Change-Id: I063e3eebc836debc01c450d8ab9f1524c9a47c56 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341633 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3288: Shuffle memlayout to make it fitJulius Werner
Another day, another overflowing RK3288 stage. There's almost 2K of space left in verstage/romstage (*gasp*, such waste!), so let's move one of them over to the bootblock. (We now have no whole kilobyte left that I can see...) BRANCH=None BUG=chromium:608439 TEST=Built Jerry Change-Id: Ice51d73ec0d89bcb1c927046be95630f177469c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb7a101daba4f4f899a9c907b29d908661aa2dae Original-Change-Id: Ib72c0b3718aac38bc97c898a74aa5757e46cef0b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341742 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/14730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: enable pp1500 and pp3000 rails as soon as possibleVadim Bendebury
The idea is that they stay low unless we know that we booted from SPI flash. As this code runs in SPI flash - it is ok to turn these rails on as soon as possible, and pp3000 rail it is essential for UART to work. Kevin rev1 and Gru designs are going to be using these pins to control these rails. Kevin rev1 had those GPIO pins routed to two chip enable signals, it is save to assert them high. BRANCH=none BUG=chrome-os-partner:51537 TEST=kevin rev0 still boots (which does not prove much) TEST=run coreboot on kevin rev1 to kernel Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131 Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341543 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHzVadim Bendebury
Previous code had several problems: * It was only initting 3 of the 4 voltage rails hooked up to PWM regulators. * It was using a PWM frequency that was out of range. Apparently from testing 300kHz is best. * It was initting all rails to .9V. On my Kevin I needed 1.1V to make booting all 6 cores / rebooting reliable. With this fix both booting all 6 cores in the kernel is reliable (if we tell the kernel not to touch the PWM) and the "reboot" command from Linux userspace is also reliable (previously it crashed in coreboot). NOTES: * Setting all rails to the same voltage doesn't make a lot of sense. We should figure out what these should _actually_ be. Presumably the little CPU rail can be lower, at least. ...and we don't use the GPU in the BIOS so we should set that lower. BRANCH=none BUG=chrome-os-partner:51922 TEST=reboot test Change-Id: I44f6394e43d291cccf3795ad73ee5b21bd949766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ac79a7cfb079d23c9d7c4899fdf18c87d05ed0e Original-Change-Id: I80996adefd8542d53ecce59e5233c553700b309f Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339151 Reviewed-on: https://review.coreboot.org/14727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/*: refactor edp driverLin Huang
rk3288 and rk3399 use same edp IP, move soc specific setting to soc/display, and move edp driver to common, so rk3399 can reuse this driver. BUG=chrome-os-partner:52460 BRANCH=none TEST= test on jerry and mighty, edp panel can work Change-Id: Ie3f3e8468b2323994af8a002413bf93b3edc8026 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64bb4b2c7ed373d9730c9aa0b0896a32164fc7ee Original-Change-Id: Ie5c15a81849a02d1c0457e36ed00fbe2d47961fb Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340504 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/spi: Allow SPI buses > 2Patrick Georgi
If SPI_BASEx is defined (for 2 < x <= 5), allow selecting it. Since the bus number translates into an offset into an array, require that all earlier buses are defined, too. Also assert() that the array is properly sized instead of blindly exceeding its bounds when called with a too big bus number. TEST=initializing bus 5 doesn't trap anymore on kevin BRANCH=none BUG=none Change-Id: I69f8ebe10854976608197a13d223ee8a555a9545 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c4af2a4ad4d6eea551653ca300ea6d04f1280919 Original-Change-Id: I27724d64d822ed0ec824a69ed611140bfbe08f5a Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Reviewed-on: https://chromium-review.googlesource.com/341034 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support saradcLin Huang
This patch add functions to configure saradc clk and get saradc's raw value for each channel. Currently add saradc to ramstage. Please refer to TRM V0.3 Part 2 Chapter 18 for this IP. BRANCH=none BUG=chrome-os-partner:51537 TEST=on kevin board, get the raw value 61 for channel 0, measure the ADC_IN0 as 0.109V, 61.0/1024 = 0.05957 0.109V/1.8V = 0.06056 Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/334177 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable arm trust firmwareLin Huang
BRANCH=none BUG=chrome-os-partner:51537 TEST=kernel is not stuck anymore and can boot into prompt, (testing with others patches) Change-Id: I74bdfa0ce608044a554bb3b06ed17b7157260294 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca4e7a50c989ae0eff270df4fa160b80a172af31 Original-Change-Id: Id95d5f282ba49981f8e33da029e8710cd4087945 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332561 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14719 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: make sure sdram top does not spill into MMIO spaceLin Huang
The base address of MMIO space is different for different Rockchip SOCs. Define them in the appropriate address map files and use the definition in common code. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I615f3cadd6d5d994b7dd1defbd10d02ad5c994da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24f941e960e4a2cfb9fc26415f56e240de3d00d9 Original-Change-Id: Ia48d75e7de546b17636cde7829ee09837b9d7ac9 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337190 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add sdram driverLin Huang
Add the sdram driver for rk3399. With this patch we can boot into depthcharge. This patch also include a config file for lpddr3-hynix-4GB that generated bases on its datasheet. Please refer to TRM V0.3 Part1 Chapter 9 for DMC. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to depthcharge on kevin Change-Id: I2afcaa3b68dbad77a5fe677b835289b675ed2bef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5d777e29942057fb7237eefa34051d1f54b19405 Original-Change-Id: Ifa1fe98a7058869518757d50678a64620610d91d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332562 Reviewed-on: https://review.coreboot.org/14716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: init the secure settingShunqian Zheng
set sdram, sram and all device to non-secure status, so we can free to do mmu operation in coreboot. bl31 will care about secure control. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338947 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable pwmLin Huang
Reuse the rockchip common pwm driver. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4 Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333255 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add gpio driverVadim Bendebury
Reuse the common gpio driver and implement some stubs in gpio.h. RK3288 has one pmu gpio while RK3399 have two. Please refer to TRM V0.3 Part2 Chapter 11 for GPIO section. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I041865ce269b0ae1f6a07e6c37d53d565a37c5ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d416ba0ce6a1ff2cf52f6b83ade601d93b40ffeb Original-Change-Id: I1d213a91ea508997b876441250743671204d7c53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332560 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: refactor gpio driverShunqian Zheng
The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP, moving the gpio code of rk3288 to common then can be reused on rk3399. BRANCH=none BUG=chrome-os-partner:51537 TEST=build and boot into chromeos on veyron_jerry Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779 Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339846 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add i2c clock driverhuang lin
This patch add i2c clock driver and reuse the common rockchip i2c driver. The i2c0,4,8 src clock from ppll, while i2c1,2,3,5,6,7 from gpll. Please refer to TRM V0.3 Part1 Page 142 for i2c clock setting. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I91822e483244d71798a1c68f14ba0a84f405a665 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 270118e44d159f6a27812fa234b34fe7ac54cbe4 Original-Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338948 Reviewed-on: https://review.coreboot.org/14711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add spi clock driverShunqian Zheng
This patch implements spi clock driver and initialize SPI flash rom for the baseboard gru. There are 6 on-chip SPI controllers inside RK3399. For SPI3, it's source clk from ppll, while the others from gpll. Please refer to CRU session of TRM for detail. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9 Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338946 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable mmuLin Huang
This patch initialize MMU and config mmu ranges for rk3399. During the bootblock phase, mark the max dram size supported(4GiB) as device memory because the mmio space start at 0xF8000000, and _sram as secure memory. After ddr setup in romstage, remark whole dram as cached memory except the _dma_coherent range. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3 Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332387 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add functions to configure ddrc freqShunqian Zheng
This patch list four frequencies for ddr controller, 200MHz, 300MHz, 666MHz and 800MHz and configure each freq by setting the DPLL dividers. By default, the clk_ddrc is from DPLL and equals to DPLL, so here we only need to set the DPLL clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2 Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340184 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support basic clock driverLin Huang
This patch initialize the PLL clocks and add function to configure cpu freq. Right now, we set the little cpu freq to 600MHz. In coreboot, we currently care about these four PLLs, o. APLL for cpu clk, where A stands for AXI, o. CPLL and GPLL are the generic PLL mainly for peripheral clk, o. PPLL is only PMU clk. For the peripheral clocks, there are thress clocks named as, aclk_perihp, aclk_perilp0, hclk_perilp1, where the 'h' and 'l' letters refer to High and Low speed. As the diagram below, the aclk_perihp always be the parent of more higher speed peripheral devices like pcie, and hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto. These three clocks can choose parent from GPLL or CPLL freely, in this patch, they are all sourced from GPLL. GPLL(594M)/CPLL(384M) APLL(600M for little core) | | `-- aclk_perihp `-- clk_core(600M == APLL) | | | | `-- periph_aclk(148.5M) `-- atclk_core(300M) | `-- periph_hclk(148.5M) `-- aclkm_core(300M) | `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M) | `-- hclk_perilp1 | | | `-- periph_hclk(99M) PPLL(594M) | `-- periph_pclk(49.5M) | | `-- pmu_pclk(99M) `-- aclk_perilp0 | `-- periph_aclk(99M) `-- periph_hclk(99M) `-- periph_pclk(49.5M) BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332386 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: use static pointers to regs as they compile to faster codeVadim Bendebury
Quoting an earlier review comment, using static structures pointers in the include file "should allow the compiler to optimize accesses better than defining it in a separate compilation unit (by being able to constant fold stuff like &rk3399_pmusgrf->field into a single address, rather than loading the symbol, loading an offset constant and adding)". Any decent compiler linker system nowadays would consolidate this definition in any case. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin successfully boots Linux kernel. Change-Id: Ibb576c7691a30f2f429651fcca133bd72710c13b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89b6f22e37f733667156f15afb8c27d8a9f07512 Original-Change-Id: Ice8d6d766a91e7f4fce553378a23b9ca593d12dd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339869 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add the GRF header fileLin Huang
The GRF(general register file) of rk3399 is divided into two sections, o. GRF, used for general non-secure system o. PMUGRF, used for always-on syosyem This patch defines the registers used for iomux/gpio/system control. BRANCH=none BUG=none TEST=emerge-kevin coreboot Change-Id: I3239793523e0f55f6661ef029c3dac9970990fb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 897d01573ea2bbe2b3091358ec3c9728ee82f8ec Original-Change-Id: I4c228ddb60c9c4056de50312dc269227fac9a7fa Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332388 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add simplest sdram to fix compiling errorShunqian Zheng
This patch is only to make building happy, the real sdram driver comes later. BRANCH=none BUG=none TEST=emerge-kevin coreboot Change-Id: I4123c3a6627d7264c615fefbb89e16c4dfb9a423 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b992a7895a72c83f57228d3abd1ae37d55e7e7b Original-Change-Id: Ie340877e828ae760169ccfa9a7099e7472d2fc26 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338944 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk*: replace UART special snowflake with standard driverPatrick Georgi
The standard uart8250mem_32 driver is now usable on ARM, so use it. BUG=none BRANCH=none TEST=see that serial firmware builds still log on serial in all stages on veyron_minnie. Also verified that a 9600 baud console is functional. Change-Id: I653b70a0d51a8d136e1da17537988f5b33c7a160 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fa27c60fd38002775072d11fca431d4788b4d1d7 Original-Change-Id: I047d74ac2d5c311f303955e62391114e16ec087a Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337551 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14319 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09soc/mediatek/mt8173: mt6391: vcore sleep voltage should be 0.7Vhenryc.chen
Vcore voltage should be 0.7V during system suspend. Because data sheet of mt6391 was not correct, need to config to 0x0 instead of 0x1. QI_VCORE_VSLEEP 00: 0.7V 01: 0.6V 10: 0.65V 11: 0.75V BUG=chrome-os-partner:52719 TEST=powerd_dbus_suspend Change-Id: Ie504ebfb7cafae85bbba7919fce1578bbfbfafb7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf15f5b63fac8968216772a8b37d2fe122414e24 Original-Change-Id: Ide53eca328c28007e2181497c888724c8a91ae93 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340540 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/oak: configure displayJitao Shi
BRANCH=none BUG=chrome-os-partner:43706 TEST=saw bootloader screen on rev4 and rev5 Change-Id: I844fed6f63467ad04d17115934a1e4724cc0b671 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2e9d57a42402631923c96e70bc2eff5c135de2fc Original-Change-Id: I748b0eac9a0aab1d38d5d44a1a50dc33d5375379 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331813 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/14690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09mediatek/mt8173: Add display driverJitao Shi
BRANCH=none BUG=none TEST=saw bootloader screen on rev4 and rev5 with CL:331813 Change-Id: Ibb01cf251276d2c059739f10e166fefd0de35460 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d52a4c486b75b99dc25657ccb6ed90f671c26d6 Original-Change-Id: I4efe439d52b5a5516145960bcffb340152bfba53 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331812 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/14689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09soc/intel/skylake: Enable another VR mailbox command for certain boardsSubrata Banik
Command List: Send command for PS4 exit fails BUG=chrome-os-partner:52355 BRANCH=glados TEST=Build and boot lars and verify no hang during active idle CQ-DEPEND=CL:*257305 Change-Id: I9ffae71b1a38433ffc48ee7be7e2a13e69ad5b87 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96f00e2d153f92339c378ce256eb7ce6824e3368 Original-Change-Id: I320ae154f3f7145811b57258ddb61b3beb584273 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341330 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14688 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09soc/intel/skylake: Output more ME status informationDuncan Laurie
Output a few more status bits from HFS/HFS2 and add some interesting bits from HFS3. BUG=chrome-os-partner:52662 BRANCH=glados TEST=boot on chell and verify ME status output Change-Id: I989b680f203678dbe28559e858faf8b4e0837481 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ea34ab019da3fff965102bcef5158ddcc154728 Original-Change-Id: Iff977c8d85b4d4dfa00b5b19bc29d11813a99b9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340390 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/14687 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-09tegra124: Align the framebuffer's bytes-per-line to 32Paul Kocialkowski
It turns out that tegra124 needs the framebuffer's bytes-per-line to be aligned to 32 for proper display. This behaviour was default before moving to edid_set_framebuffer_bits_per_pixel. This fixes display on nyan_big. Change-Id: Ie81b395fca23f3648ea7cd1df51152faea864c9a Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14564 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra132, tegra210: Align the framebuffer's bytes-per-line to 64Paul Kocialkowski
It turns out that tegra132 and tegra 210 need the framebuffer's bytes-per-line to be aligned to 64 for proper display. This behaviour was default before moving to edid_set_framebuffer_bits_per_pixel. Change-Id: I46dadcf36e1c50e9649121ee6fa9cdf6134a531e Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14734 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09tegra132, tegra210: Fix "becasue" typo in commentsPaul Kocialkowski
This renames "becasue" occurrences to "because". Change-Id: I7862ce6a865cb1525ca1cef69c2eb1e90cc76a9d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14735 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-05-09xip: Do not pass --xip for early stages if CAR supports code executionFurquan Shaikh
On modern x86 platforms like apollolake, pre-RAM stages verstage and romstage run within the cache-as-ram region. Thus, we do not need to pass in the --xip parameter to cbfstool while adding these stages. Introduce a new Kconfig variable NO_XIP_EARLY_STAGES which is default false for all x86 platforms. Apollolake selects this option since it supports code execution with CAR. Change-Id: I2848046472f40f09ce7fc230c258b0389851b2ea Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06soc/apollolake/lpc: Allow configuring SERIRQ via devicetreeAlexandru Gagniuc
Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ continuous mode. Why they do that is beyond me, but the way we implement it on apollolake is via devicetree. Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06soc/apollolake/lpc_lib: Add utility to configure LPC padsAlexandru Gagniuc
Change-Id: Iaf325863681ad9b8b5d7662a9d267488b8fdf008 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06soc/apollolake/lpc: Open I/O to LPC based on resource allocationAlexandru Gagniuc
Besides a number of fixed memory windows, Apollolake supports opening a configureable 64 KiB MMIO window, as well as four PMIO windows to the LPC bus. Open up these windows dynamically, based on how resources were allocated to the child LPC devices. Change-Id: I170e861693cb6fd1be38889adc951f197a13460f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06Revert "soc/intel/apollolake: Enable LPC bus interface"Alexandru Gagniuc
This reverts commit e976bd44692d2adb320a1256f1b6bfaa6469108a. The LPC resource allocation will be completely reworked in subsequent patches. The most straightforward approach is to start by reverting the existing code. Change-Id: I2475542b79817020d4c956f22ed5856f05046b16 Reviewed-on: https://review.coreboot.org/14583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06soc/intel/apollolake: fix incorrect bdsm -> tolud memory resourcesAaron Durbin
The wrong base address was being used for the region of memory between BDSM and TOLUD. This resulted in a very large reserved region starting at TOLUD instead of BDSM. Change-Id: I41d06267ffa93ea47aa059f4ddb7b9c349e51583 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14628 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06soc/intel: indicate to build system that XIP_ROM_SIZE isn't usedAaron Durbin
The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets. Therefore, indicate as such so that romstage can be placed in cbfs less rigidly. Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14626 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06{cpu,soc}/intel: remove unused smm_init() functionAaron Durbin
There used to be a need for an empty smm_init() function because initialize_cpus() called it even though nothing called initialize_cpus(). However, garbage collection at link time is implemented so there's no reason to provide an empty function to satisfy a symbol that is completely culled during link. Remove it. Change-Id: Ic13c85f1d3d57e38e7132e4289a98a95829f765a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14605 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/skylake: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I5c4674ed258922b6616d75f070df976ef9fad209 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14597 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06soc/intel/broadwell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I74c81c5d18dff7a84bfedbe07f01e536c0f641fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14595 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-06soc/intel/apollolake: convert to using common MP initAaron Durbin
In order to reduce duplication of code use the common MP initialization flow. Change-Id: I8cfb5ba6f6a31fecde2ce3bf997f87c4486ab3ab Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14594 Tested-by: build bot (Jenkins) Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/braswell: convert to using common MP and SMM initAaron Durbin
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I65beefec53a29b2861433bc42679f3fa571d5b6a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14593 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-06soc/intel/fsp_broadwell_de: convert to using common MP initAaron Durbin
In order to reduce duplication of code use the common MP initialization flow. Change-Id: I2a7c628cfae7cf6af6e89fa8fc274f59127ff7c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14592 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-05-06soc/intel/apollolake: Correct PCI write size in romstageFurquan Shaikh
1. PCI command reg write should be 16-bit. 2. HPTC reg write should be 8-bit. Also, use macros instead of hard-coded values. Currently, the macros are defined in romstage.c, but if more P2SB macros are added, it would be good to move them to a separate header file. Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14613 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 22:22:27 +0000