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2020-07-06mb/google/zork: Add USB2 phy tuning parameter for SI tuningChris Wang
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength. BUG=b:156315391 TEST=Build, verified the tuning value been applied on Trembyle. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I3d31792d26729e0acb044282c5300886663dde51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/amd/common: Fix missing gpio_banks.h includeKyösti Mälkki
Change-Id: I2c92280f3bbd80bd7a0d3abfb2fddcef997e144e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/amd/picasso/memlayout: Verify bootblock is 16-bit alignedRaul E Rangel
The bootblock must be 16-bit aligned for it to boot. BUG=b:159081993 TEST=Made sure trembyle still compiles. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart InitMaulik V Vaghela
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it. Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot BUG=None BRANCH=None TEST=FSP is able to push debug logs on UART with this setting Cq-Depend: TBD Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-07-06soc/amd/picasso: Use PSP Sx command only for S3Marshall Dawson
Skip sending MboxBiosCmdSxInfo for sleep states other than S3. The PSP only acts on S3 and ignores all others. As a result, the command register is not cleared upon return and coreboot reports a timeout. BUG=b:153622879 TEST=Use halt from command line, verify command skipped. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-04soc/intel/xeon_sp/cpx: update HOB display codeJonathan Zhang
Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB. Build hob display into romstage, in addition to ramstage. Memory map HOB data is a big structure. Update the soc_display_memmap_hob() to assist trouble shooting of FSP interface. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42841 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04soc/intel/xeon_sp: Add read CPU PPIN MSR functionJohnny Lin
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP Tioga Pass and Delta Lake. Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04soc/intel/tigerlake: Remove unused EHL DID from TGL SoCSubrata Banik
TEST=Able to build and boot TGLRVP. Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-03soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu
A UPD HybridStorageMode allows a platform to dynamically configure the PCIe strap configuration required if an Optane device is connected. The strap configuration is done by HECI commands between FSP and CSE to override the default PCIe strap value, and the updated strap value is stored in SPI RW data to be used on the next boot. CSE Lite supports the strap override when running on CSE RW partition, while CSE RO partition does not support it because CSE RO is not allowed to access SPI RW data. The strap override failure on CSE RO causes FSP not initializing PCH Clkreq and PCIe port mapping and this results NVMe and Optane initialization failure. By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is done by the default PCIe configuration and Optane is detected as a single NVMe storage device on CSE RO boot in recovery mode. Both NVMe and Optane devices detection as well as OS installation to these storage devices are verified on CSE RO boot in recovery mode. BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03soc/amd/common: fix eSPI virtual wire polarity encodingAaron Durbin
eSPI interrupts are active level high. The eSPI polarity register in the chipset inverts incoming signals if the corresonding bit is 0 in the register. Therefore, all active high (edge or level) virtual wire interrupts need to ensure they are not inverted. And really the sender of the interrupts should be conforming to the the eSPI spec. As such inverting any signals should not be necessary, but this register in the chipset allows for fixing up those misbehaviors. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03drivers/intel/pmx_mux: Remove redundant declarationKyösti Mälkki
Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41871 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03soc/intel/common: Only touch Time Window Tau bits in supported SoCsTim Wawrzynczak
The Time Window Tau bits are only supported by Comet Lake/Cannon Lake onwards, so skip setting those bits for earlier SoCs. Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-07-02soc/amd/picasso: Add support for generating I2S machine deviceFurquan Shaikh
This change adds support in ACP device driver to generate I2S machine device (AMDI5682) in SSDT. It expects mainboard to provide chip config `dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the device. BUG=b:157603026 TEST=Verified that I2S machine device is correctly generated for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252557 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP deviceFurquan Shaikh
This change adds support for .acpi_name and .acpi_fill_ssdt_generator device operations for the ACP device. BUG=b:157603026 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I84bb8150dada99def85b685535706aa609de227f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252556 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02soc/amd/common: fix SPI bar resource usageAaron Durbin
The ACPI code was not masking off the correct bits for publishing the SPI bar to the OS. It resulted in a dmesg messagelike: system 00:00: [mem 0xfec10002-0xfec11001] has been reserved And /proc/iomem entry fec10002-fec11001 : pnp 00:00 These addresses are wrong because they are including bits of a register that are not a part of the address. Moreover, the code does not publish the eSPI register area either. The eSPI registers live at 0x10000 added to the SPI bar. Lastly, both regions are less than a page so only report a page of usage for each. Stoney Ridge's SPI bar register defines the address as 31:6 while Picasso's SPI bar register defines the address as 31:8. Use Picasso's valid mask for both cases because no one is assigning addresses that are aligned to less than 256 bytes. With the fixes, dmesg reports: system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved And /proc/iomem indicates: fec10000-fec10fff : pnp 00:00 fec20000-fec20fff : pnp 00:00 BUG=b:160290629 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/42959 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entryJamie Ryu
This is a W/A to avoid a communication issue with CSE Lite over Heci interface. This will help to avoid boot failures with CSE Lite until the permanent fix is available. BUG=b:159884143 TEST=build and boot volteer with serial and non-serial image Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/cannonlake: make satahotplug user configurable via devicetreeJonas Loeffelholz
Hook up the FSP UPD Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42803 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/common/cpu: Don't set any TCC settings if offset is 0Tim Wawrzynczak
Many previous versions of this function would return early if tcc_offset is 0. This adds that logic back in. Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-07-01soc/intel/skylake: Update ASL syntax in xhci.aslEdward O'Callaghan
Use some defines as well for clarity. Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42898 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4John Zhao
This change adds Platform-Wide _OSC capabilities for native USB4 support. There is Engineering Change Request (ECR) with _OSC addition for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18 as native USB4 support. The OS sets this bit to indicate support for an OSPM-native USB4 Connection Manager which handles USB4 connection events and link management. The OS use the _OSC mechanism and the bit defined in this ECR to obtain configuration and connection management capabilities of USB4 connections. This change also fixs the byte index for the DWord-addressable field CDW3 from the capabilities buffer. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/42821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-01ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30soc/amd/common/gpio: Clear interrupt and wake status when configuring padsFurquan Shaikh
This change clears interrupt and wake status for a pad when configuring it. This ensures that stale interrupts/wake notifications are flushed out and do not cause spurious wakes in future suspends. BUG=b:159944426 Change-Id: Ia4ebd975312a4136f1d0690d7af7372615e31f0f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Add new helper macro PAD_CFG_STRUCT_FLAGSFurquan Shaikh
`flags` field of soc_amd_gpio structure is set only for SCI and SMI configurations. This change adds a new helper macro PAD_CFG_STRUCT_FLAGS that allows setting of all soc_amd_gpio members including `flags` field. This can be used directly by PAD_SCI and PAD_SMI. For all other pad configurations, PAD_CFG_STRUCT macro uses PAD_CFG_STRUCT_FLAGS with flags set to 0. This allows dropping of redundant parameter 0 for flags for all other pad configurations. BUG=b:159944426 Change-Id: I835b62f5502375ffc4215548b51338a67546d699 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/gpio, mb/{amd,google}: Configure pads using a single entry in GPIO ↵Furquan Shaikh
configuration table Currently, for Stoneyridge and Picasso mainboards, pads that are configured for SCI/SMI/WAKE need to have multiple entries in the configuration table - one for PAD_GPI and other for the special configuration that is required. This requires a very specific ordering of pads within the table and is prone to errors because of conflicting params provided to the different entries for the same pad. This also does not work very well with the concept of override GPIOs where the entry in base table is overridden with the first matched entry from the override table. This change updates the way GPIO configuration is handled for special routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of soc_amd_gpio structure in the macros performing these configurations. Also, program_gpios() is updated to perform a write to GPIO control register instead of read-modify-write. This is because mainboard is expected to provide only a single configuration entry for each pad within a given table. Thus, there is no need to preserve earlier configuration. Mainboards that were providing multiple entries for a single pad are updated accordingly. BUG=b:159944426 Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Use gpio_setbits32()Furquan Shaikh
Some codepaths want to set selected bits of a hardware register to match those of a given variable in memory. Provide a helper function for this purpose and use it in gpio_set(), gpio_input_pulldown() and gpio_input_pullup(). This change also adds GPIO_PULL_MASK and updates GPIO_OUTPUT_MASK to include all bits dealing with pull and output respectively. Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30soc/amd/common/gpio: Add macros for setting fields of soc_amd_gpioFurquan Shaikh
This change adds helper macro PAD_CFG_STRUCT for setting the fields of `soc_amd_gpio`. Additionally, macros are added for different operations i.e. pull, output, trigger, int_enable, event_trigger, wake_enable, debounce, etc. All GPIO configuration macros are updated to use PAD_CFG_STRUCT instead of setting the fields directly. BUG=b:159944426 Change-Id: I03535d2da0c05f72c4163fa30d72f9c6df44908b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42872 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/lpc: Skip SERIRQ setup when using eSPIMarshall Dawson
BUG=b:157984427 TEST=check value of PMx054 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2ca14c137ed784a1a7cfeed969719f46fc8230f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-30soc/amd/common/gpio: Rename GPIO debounce macrosFurquan Shaikh
This change updates the macros for GPIO debounce to add _DEB_ in the name. This is done to make the names consistent with rest of the GPIO control field names. BUG=b:159944426 Change-Id: Ic47678108c871c5f1cd0d512783230f18adf3484 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Update the macros for interrupt and pad filteringFurquan Shaikh
This change renames GPIO macros as follows: 1. Pad filtering macros are renamed to GPIO_TRIGGER_ and GPIO_ACTIVE_. This determines the filtering applied on the input signal at the pad. 2. Interrupt enabling macros are renamed to GPIO_INT_ENABLE_. _INT_ is dropped from pad filtering macros because the filtering applies to the input signal irrespective of how it is routed. It is applied at the pad not only for GPIO interrupts but also for other routes i.e. SCI, SMI, etc. BUG=b:159944426 Change-Id: Id0ad770be77409aaaae4cc135945e2815ce97030 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42870 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/amd/common/gpio: Make macro names for GPIO flags consistentFurquan Shaikh
`soc_amd_gpio` structure uses a flag field to store additional information about GPIO configuration that does not end up directly in the GPIO control register. However, the naming for these flags is not consistent across event triggers and special configurations. This change updates the flag names to be consistent (starting with GPIO_FLAG_*) and adds some helper functions for GPIO events. In the following CLs, more changes will be made to drop some of the special flags which are not really required. BUG=b:159944426 Change-Id: Idca795c3e594eb956d297d5ba5d08f75b5563ee5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/cannonlake: Add UWES ASL into xhci.aslEdward O'Callaghan
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`. This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:159187889 BRANCH=none TEST=none Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30jasperlake: enable tcc_offset functionalitySumeet R Pawnikar
This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset value to new value in devicetree. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30tigerlake: enable tcc_offset functionalitySumeet R Pawnikar
This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset to new value in devicetree. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I36b0d6aad4be8a9cbb145dcd66d65235d3f6ac35 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-30soc/amd/common/gpio: Drop unused macro GPIO_TRIGGER_INVALIDFurquan Shaikh
This change drops unused macro GPIO_TRIGGER_VALID from gpio_banks.h. BUG=b:159944426 Change-Id: Ie115f37893d9ba190bab56cf8b037febd8b5f4b5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
Add CpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from devicetree. This UPD allows platforms with soldered down SoC to skip CPU replacement check to avoid a forced MRC traning. TEST=boot and verified with volteer Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1429981 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Iea3801585e8c294fb889a8137b534bb932696025 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42836 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdtFelix Held
Found-by: Coverity CID 1429980 Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-29soc/amd/picasso/soc_util: add comment on the silicon and soc typesFelix Held
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-29soc/amd/common: Refactor GPIO SCI/SMI interruptsKyösti Mälkki
Change-Id: Ib2c7cd70ab38d0d8e745b0a611b780d2b0b8dc5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-29soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enableKyösti Mälkki
There is no GPIO_63 but the register position is used for interrupt controls. Change-Id: I754a2f6bbee12d637f8c99a9d330ab0ac8187247 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42686 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL takes advantage of the property. Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_opsWilliam Wei
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail). BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt socJonathan Zhang
The previous Intel CPX-SP FSP release was ww20 release. The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end flow of using memory training data to generate FSP_NV_STORAGE HOB and using memory training data passed from bootloader to skip memory training, works now. This saves 8 minutes of boot time (with FSP verbose logging enabled on DeltaLake server). This release also adds UPD parameters to support IIO bifuration. The ww24 release has following updates: a. Removed a number of unnecessary UPD parameters, such as mmiolSize, mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate. b. Added UPD parameters to support PCIe ports configuration. c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit fields, in addition to PCIe resource memory base/limit fields. With ww24 release, the issue with PCIe link training persists. On YV3 config A, the onboard NIC card has x4 connection to port 2D. This NIC device is not recognized by FSP. Corresponding soc/intel/xeon_sp/cpx change is made: * There are changes in PLATFORM_DATA structure, so hob_display.c is updated. * There are changes in UPD parameters, so romstage.c is updated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28soc/amd/common: Allow runtime mapping of ACPIMMIO banksKyösti Mälkki
Future implementation of verstage running on PSP will have access to some of the ACPIMMIO banks, but banks will be mapped runtime at non-deterministic addresses. Provide preprocessor helpers to accomplish this. Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28soc/intel/common: add TCC activation functionalitySumeet R Pawnikar
This enables to configure the Thermal Control Circuit (TCC) activation value to new value as tcc_offset in degree Celcius. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action before CPU temperature reaches maximum operating temperature TjMax value. Also, cleanup local functions from previous intel soc specific code base like for apollolake, broadwell, skylake and cannonlake. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-28soc/xeon_sp/cpx: Define MSR PPIN related registersJohnny Lin
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/ Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-28soc/amd/picasso/soc_util: rework reduced I/O chip detectionFelix Held
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort connectivity. While Dali can either be fused-down PCO or RV2 silicon, Pollock is always RV2 silicon. Since we have all boards using this code in tree right now, soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku(). Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 15:57:04 +0000