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2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04soc/dmp: Drop leftover fileKyösti Mälkki
Change-Id: I6994b48b48fb7177b9ae32825dcd9af099b85410 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-04soc/broadcom/cygnus: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id41279a1cdc7c68d3dcc44e238863f2f4a452499 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/imgtec/pistachio: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ia36b4ef7d66c50a044bc51f452ac8b7c7ff14323 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/marvell/mvmap2315: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I6db25850d46ea3a940ea2a6f263303d4b5304cb3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/mediatek/mt8173: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ifadb894f98ce60cf0778de7fbcec67d125e48fd6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/samsung: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ibf21100eb2232932ea52740bd5250319d3c9adfa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/rockchip: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Idf47ea3b29c3fab7256d7a6722c7978594001d8d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04soc/intel/denverton_ns: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I15e624b40d11f61a3870a6083be82d062690498d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/skylake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26541 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04soc/intel/apollolake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id6bcf98892c1944ec9c7e637f63c4c05fe9a0c07 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/braswell: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/fsp_broadwell_de: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I68c455d4bc524c2dd2d3ba87ab6641e70c78521c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04soc/intel/fsp_baytrail: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-03soc/intel/apollolake: Add Page table mapping for System MemoryHannah Williams
Since we do not know before hand the memory range initialized by FSP memory init until it completes and as memory gets accessed from within FSP memory init to migrate FSP from CAR to memory, we need to add this mapping in coreboot. Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/26745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-02soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ modeAamir Bohra
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/26730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-06-01soc/intel/cannonlake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iea56a6560bb23d48d19211304e57fc08e1c27fd6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26584 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01soc/intel/broadwell: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26583 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-01soc/amd/stoneyridge: Add ACPI device name lookupMarc Jones
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup function. BUG=b:80280671 TEST=Add ACPI method to specific GPP bridge. Boot and verify method with ACPI dump. Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/26698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-31soc/intel/broadwell: decouple PEI memory struct from coreboot headerMatt DeVillier
Recent changes to field lengths in include/memory_info.h resulted in a mismatch between the memory_info struct the MRC blob writes to and the struct used by coreboot to parse out data for the SMBIOS tables. This mismatch caused type 17 SMBIOS tables to be filled incorrectly. The solution used here is to define the memory_info struct as expected by MRC in the pei_data header, and manually copy the data field by field into the coreboot memory_info struct, observing the more restrictive lengths for the two structs. Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly populated. Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/26598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-31soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31soc/intel/skylake: Select common P2SB codeSubrata Banik
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB to include common p2sb code block. BUG=b:78109109 BRANCH=none TEST=Build and boot EVE. Change-Id: I3f6aa6398e409a05a35766fb7aeb3aa221dd3970 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26165 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-30soc/intel/cannonlake: Enable IDT and expection handling support for all stagesAamir Bohra
Change-Id:I4146a040e5e43bed7ccc6cb0a7dc2271f1e7a8ea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/26661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-29src/soc: Add and update license headersMartin Roth
This change adds and updates headers in all of the soc files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all soc directories. Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-28fsp_broadwell_de: Select TSC_MONOTONIC_TIMER by defaultDavid Hendricks
This is currently selected by each derivative board's Kconfig even though it's really an SoC-specific option. Change-Id: Iad135261915a0857c53c18aaebde7e46c97a8f40 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26344 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28intel/skylake: nhlt: Update Max98373's capture formatSathyanarayana Nujella
Max98373's NHLT capture configuration is used for IV feedback for DSM algorithm. Feedback is 4-channel data. Without this configuration below error is seen in dmesg: [ 315.784250] snd_soc_skl 0000:00:1f.3: Blob NULL for id 0 type 3 dirn 1 [ 315.784263] snd_soc_skl 0000:00:1f.3: PCM: ch 4, freq 48000, fmt 32 So, update nhlt configuration accordingly. BUG=b:79362472 TEST=Audio playback works with IV feedback enabled Change-Id: I75434a63fe030ed9bb963c6d300d833a8e7d2d66 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26384 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28soc/intel/quark: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I102c9b9b1066064589149388d5ebbcd6d0d81fa7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-28soc/qualcomm: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ib7bcfefaecc053a1ed28d708a614acb81207bccf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-28soc/nvidia: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I065ed3a0deab2f59e510717f5d52beb2a62e900d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-27soc/intel/cannonlake: Select common XHCI codeSubrata Banik
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI to include common xhci code block. BUG=b:78109109 BRANCH=none TEST=Build and boot cnlrvp Change-Id: I7f1e59792159dae5835fbbe7fcb1604fc01893ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27grunt: Wire up the EC SMI handlerRaul E Rangel
This won't actually get called yet since the GPIO pin has not been configured as SMI. BUG=b:80295434 TEST=grunt: Made sure events could be processed. Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-27amd: Don't call halt() when in SMMRaul E Rangel
This copies what Intel does. BUG=b:80295434 TEST=grunt: Made sure that the S5 SMI interrupt gets fired. Change-Id: I7874824cad01054c6bdeff12d248e671f27be030 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-25soc/amd/stoneyridge: Increment boot_count on non-S3 bootsDaniel Kurtz
Increment the boot_count from romstage when not resuming from S3. BUG=b:80266624 TEST=firmware_EventLog TEST=boot, then: mosys eventlog list | grep boot 1 | 2018-05-24 16:51:42 | System boot | 1 reboot mosys eventlog list | grep boot 1 | 2018-05-24 16:51:42 | System boot | 1 6 | 2018-05-24 16:52:34 | System boot | 2 Change-Id: Ideec9da809e494fb0ea073f648540285972f8238 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26525 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25soc/amd/stoneyridge: Record ACPI Wake events in ELOGDaniel Kurtz
We are already reporting the Wake source, but we must also report the ACPI wake itself. BUG=b:79865267 TEST=firmware_EventLog Change-Id: Id26dff46379800a63ab9b77f135d23c6382f77e6 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26522 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25soc/intel/cannonlake: Reduce STACK_SIZE to 4KiBSubrata Banik
TEST=Build and boot cannonlake rvp till OS. Change-Id: I5369afd0d1d66e25d210416730a2c1c91ca8e94a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-24soc/intel/baytrail: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24src: Remove space after `defined`Elyes HAOUAS
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26460 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23mb/google/kahlee/dsdt.asl: Add method _SWSRichard Spiegel
_SWS is the recommended method of wake source retrieval. Now that PM1I and GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code. BUG=b:76020953 TEST=Build grunt Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23stoneyridge: Store wake parameters in NVSRichard Spiegel
ACPI _SWS needs information on PM1 and ACPI events (though events can be read directly). Unfortunately PM1 is cleared in normal path and in resume path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS. BUG=b:75996437 TEST=Build and boot grunt recording serial. Run suspend stress test, after 3 resumes closed file and examined for the message indicating what was being saved to NVS. Two different path, normal boot (first boot) and resume path had different PM1. Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23soc/amd/common/block/pci: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I82089475eb43d58303d1091f35aee06f1f04b4a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-23soc/amd/stoneyridge/: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-05-22soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI InitSrinidhi N Kaushik
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table entry for this range which caused a page fault. Since this test is anyway not exhaustive, we will skip the memory test in FSP. There is an option to do PCIe power sequence from within FSP if provided with the GPIOs used for PERST to FSP. Since we do this from coreboot, will skip the PCIe power sequence done by FSP. FSP does not know what the clock requirements are for the device on SPI bus, hence it should not modify what coreboot has set up. Hence skipping SPI clock programming in FSP. CQ-DEPEND=CL:*627827 BUG=b:78599939, b:78599576, b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26284 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22soc/nvidia/tegra(124|210): Add distclean targetsMartin Roth
Add distclean targets so these can be called by the junit.xml test target needed for jenkins testing. Change-Id: I5991b43503da1778a6d74a57fbc0daf862e570d7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-22amd/stoneyridge: Increase SMM reserved memoryMarshall Dawson
Add 64KB to the reserved memory used for stage_cache. This corrects an error observed when using a debug build of the AGESA blob. Messages on initial boot AGESA: Saving stage to cache Error: Can't add stage_cache 57a9e101 to imd and during resume AGESA: Loading stage from cache Error: Can't find stage_cache 57a9e101 in imd TEST=boot/suspend/resume Grunt with debug and release builds BUG=b:79154155 Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22src: Remove non-ascii charactersMartin Roth
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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