| Age | Commit message (Expand) | Author |
|---|
| 2020-02-12 | soc/intel/{skl, common}: Move ME Firmware SKU Types to common code | Sridhar Siricilla |
| 2020-02-11 | vendorcode/intel: Remove Ice Lake FSP Bindings | Johanna Schander |
| 2020-02-11 | soc/intel/common/block/lpc: Add lpc_get_fixed_io_decode | Wim Vervoorn |
| 2020-02-09 | intel/stm: Add platform opt-in Kconfig | Nico Huber |
| 2020-02-09 | soc/intel/tigerlake: add memory configuration support | Nick Vaccaro |
| 2020-02-09 | soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_messa... | Sridhar Siricilla |
| 2020-02-09 | soc/intel/common: Add description to HMRFPO status | Sridhar Siricilla |
| 2020-02-09 | soc/intel/common: Rename functions for consistent naming | Sridhar Siricilla |
| 2020-02-09 | soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC | Sridhar Siricilla |
| 2020-02-07 | sc7180: clock: Fix QUP DFSR configuration for perf levels | Taniya Das |
| 2020-02-04 | soc/intel: Add get_pmbase | Eugene Myers |
| 2020-02-04 | soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle | Aamir Bohra |
| 2020-02-04 | soc/intel: Remove duplicate CPUID entry | Subrata Banik |
| 2020-02-04 | soc/amd: unify SMBus support | Aaron Durbin |
| 2020-02-01 | soc/intel/tigerlake: Configure TCSS xHCI and xDCI | Wonkyu Kim |
| 2020-01-31 | soc/amd/picasso: move to using smbus_host.h definitions | Aaron Durbin |
| 2020-01-31 | soc/amd/picasso: use SMBus timeout in compilation unit | Aaron Durbin |
| 2020-01-31 | soc/amd/picasso: use SMBus speed in compilation unit | Aaron Durbin |
| 2020-01-31 | soc/amd/stoneyridge: move to using smbus_host.h definitions | Aaron Durbin |
| 2020-01-31 | soc/amd/stoneyridge: use SMBus timeout in compilation unit | Aaron Durbin |
| 2020-01-31 | soc/amd/stoneyridge: use SMBus speed in compilation unit | Aaron Durbin |
| 2020-01-30 | soc/intel/common/systemagent: Add Kconfig guard | Andrey Petrov |
| 2020-01-30 | soc/intel/common/block/lpc: Add CMP-H LPC IDs | Gaggery Tsai |
| 2020-01-29 | soc/intel/skylake/acpi/dptf: Remove processor throttling controls | Wim Vervoorn |
| 2020-01-29 | amdblocks/biosram: Do small reformatting | Marshall Dawson |
| 2020-01-29 | soc/intel/tigerlake: Disable image clocks | Wonkyu Kim |
| 2020-01-28 | soc/intel/tigerlake: Enable DP ports according to board design | Wonkyu Kim |
| 2020-01-28 | drivers/spi/spi_flash: remove spi flash names | Aaron Durbin |
| 2020-01-28 | commonlib: Add commonlib/bsd | Julius Werner |
| 2020-01-26 | soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet | Subrata Banik |
| 2020-01-26 | soc/intel/skylake: Add _SEG/_UID name variables | Subrata Banik |
| 2020-01-26 | soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device | Subrata Banik |
| 2020-01-25 | soc/intel/tigerlake: Add IPU in ACPI | Wonkyu Kim |
| 2020-01-25 | soc/intel/tigerlake: Configure ClkReq according to mainboard design | Wonkyu Kim |
| 2020-01-25 | soc/intel/tigerlake: Add GPIO helper function | Shaunak Saha |
| 2020-01-25 | soc/intel/tigerlake: Fix GPIO communities | Shaunak Saha |
| 2020-01-24 | soc/intel/skylake: Remove unused ICH memory reference | Subrata Banik |
| 2020-01-24 | soc/intel/skylake: Move pci_irqs.asl from SA to PCH | Subrata Banik |
| 2020-01-24 | soc/intel/tigerlake: Enable SATA | Wonkyu Kim |
| 2020-01-23 | soc/intel/common: Update SA bit fields as per EDS | Subrata Banik |
| 2020-01-22 | soc/intel/tigerlake: enable gpio dual route support | Nick Vaccaro |
| 2020-01-22 | soc/intel/tigerlake: Update fsp_params for TGL | Srinidhi N Kaushik |
| 2020-01-22 | soc/intel/tigerlake: Update GPIO config | Ravi Sarawadi |
| 2020-01-22 | soc/intel/common: Add Elkhartlake Device IDs | Tan, Lean Sheng |
| 2020-01-22 | soc/intel/tigerlake: Update interrupt info | Wonkyu Kim |
| 2020-01-22 | {soc,southbridge}/*/*/acpi: Add possibility to disable S4 | Wim Vervoorn |
| 2020-01-20 | soc/amd/picasso: Add SMMSTORE support | Marshall Dawson |
| 2020-01-20 | soc/amd/stoneyridge: Add SMMSTORE support | Matt DeVillier |
| 2020-01-18 | soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs | Gaggery Tsai |
| 2020-01-18 | soc/intel/cannonlake: Add chip config for SATA strength | Jamie Chen |
