coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-08	soc/amd/picasso: establish full early caching memory map	Aaron Durbin
2020-06-08	spd/lp4x: Set manufacturer part name to blank (0x20)	Furquan Shaikh
2020-06-07	soc/intel/baytrail,braswell,broadwell,quark: Select COMMON_FADT	Kyösti Mälkki
2020-06-07	soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntax	Venkata Krishna Nimmagadda
2020-06-07	soc/amd/picasso/cpu.c: Make comment clearer	Raul E Rangel
2020-06-07	soc/intel/jasperlake: Add JSL PMC as 'hidden' PCI device	Tim Wawrzynczak
2020-06-07	mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()	Kyösti Mälkki
2020-06-07	acpi,soc/intel: Make soc/motherboard_fill_fadt() global	Kyösti Mälkki
2020-06-07	soc/amd/picasso: Remove unnecessary includes from pmutil.c	Martin Roth
2020-06-06	src: Use pci_dev_ops_pci where applicable	Angel Pons
2020-06-06	soc/amd/picasso: Add device operations for UART MMIO devices	Furquan Shaikh
2020-06-06	src: Remove unused 'include <cpu/x86/mtrr.h>'	Elyes HAOUAS
2020-06-06	soc/amd/picasso: Use MSR_CSTATE_ADDRESS	Raul E Rangel
2020-06-06	soc/amd/picasso: Remove call to setup_bsp_ramtop	Raul E Rangel
2020-06-06	src: Remove unused '#include <cpu/x86/smm.h>'	Elyes HAOUAS
2020-06-06	soc/intel/tigerlake: Add CPU ID for TGL B0	Jamie Ryu
2020-06-06	lp4x: Add new memory parts and generate SPDs	Furquan Shaikh
2020-06-06	soc/intel/jasperlake: Generate LP4x SPD files using gen_spd.go	Furquan Shaikh
2020-06-06	soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.go	Furquan Shaikh
2020-06-06	arch/x86: Declare permanent_smi_handler()	Kyösti Mälkki
2020-06-06	soc,southbridge/intel: Control SMI related FADT entries	Kyösti Mälkki
2020-06-06	soc/intel/xeon_sp/cpx: set up cpus	Jonathan Zhang
2020-06-05	soc/amd/common/spi: add and use define for last FIFO position	Felix Held
2020-06-05	soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devices	Furquan Shaikh
2020-06-04	soc/amd/picasso/Makefile: Allow absolute path for picasso firmware	Raul E Rangel
2020-06-04	soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration	Jonathan Zhang
2020-06-04	soc/amd/picasso: fix iomap for ACPI_PM	Kangheui Won
2020-06-03	soc/amd: Use mp_cpu_bus_init()	Kyösti Mälkki
2020-06-03	soc,southbridge/amd: Remove some explicit zero-initializers	Kyösti Mälkki
2020-06-03	soc/intel/quark/memmap: Add missing 'include <cpu/x86/mtrr.h>'	Elyes HAOUAS
2020-06-03	soc/intel/jasperlake: Update C-States info	Ronak Kanabar
2020-06-03	soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-06-03	soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-06-03	soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-06-03	soc/amd/picasso/acpi: Add missing eMMC device	Raul E Rangel
2020-06-03	soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers	Raul E Rangel
2020-06-03	soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITS	Tim Wawrzynczak
2020-06-03	soc/intel/tigerlake: update elog to include CSME reset causes	derek.huang
2020-06-02	soc/intel/common/{pch,sata}: Remove SATA common code driver	Subrata Banik
2020-06-02	soc/amd/picasso: Install AGESA ACPI tables	Matt Papageorge
2020-06-02	soc/intel/cannonlake: Add RP configuration settings	Christian Walter
2020-06-02	soc/intel/jasperlake: Update camera_clock_ctl.asl to ASL2.0 syntax	V Sowmya
2020-06-02	soc/intel/jasperlake: Update gpio_op.asl to ASL2.0 syntax	V Sowmya
2020-06-02	soc/intel/jasperlake: Update pch_hda.asl to ASL2.0 syntax	V Sowmya
2020-06-02	soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax	V Sowmya
2020-06-02	soc/intel/jasperlake: Update platform.asl to ASL2.0 syntax	V Sowmya
2020-06-02	vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release	Jonathan Zhang
2020-06-02	soc/xeon_sp/skx: Define MSR PPIN related registers	Johnny Lin
2020-06-02	src: Remove unused '#include <cbfs.h>'	Elyes HAOUAS
2020-06-02	src: Remove redundant includes	Elyes HAOUAS