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2020-05-18Remove new additions of "this file is part of" linesElyes HAOUAS
Change-Id: I96dfa5b531842afcf774dd33c2dfa532b5d329c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-05-18soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD readWim Vervoorn
Reading the SPD using the SMBUS routines takes a long time because each byte or word is access seperately. Allow using the i2c read eeprom routines to read the SPD. By doing this the start address is only sent once per page. The time required to read a DDR4 SPD is reduced from 200 msec to 50 msec. BUG=N/A TEST=tested on facebook monolith Change-Id: I44e18b8ba72e1b2321f83402a6a055e2be6f940c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-18soc/mediatek: dsi: adjust hfp_byte and hbp_byte if too smallPaul Ma
If panel has too small hfp or hbp, hfp_byte or hbp_byte may become very small value or negative value. When very small value or negative value is used, the panel will be scrolling or distorted. This patch adjusts their values so that they are greater than the minimum value and keep total of them unchanged. DSI transfer HBP or HFP, There are some extra packet. ex. packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte) and (next)hs packet header(4 byte). So the min hfp_byte is 2 when HFP = 4. This is equivalent to the Linux kernel DSI change in: https://chromium-review.googlesource.com/c/chromiumos/third_party/ kernel/+/2186872 BUG=b:144824303 BRANCH=kukui TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its hbp only 6), the panel can display without scrolling or distortions. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18jasperlake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Jasperlake SoC based platforms. BRANCH=None BUG=None TEST=Built for jasperlake system Change-Id: I9b725d041dcb8847f83ec103e58b9571b4c596ac Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18soc/intel/common: add processor power limits control supportSumeet R Pawnikar
Add processor power limits control support under common code. BRANCH=None BUG=None TEST=Built and checked this entry on Volteer system, cat /sys/class/powercap/intel-rapl/intel-rapl\:0/* Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-18soc/amd/picasso: Set VERSTAGE_ADDR for picassoRaul E Rangel
By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This causes problems in a non-xip environment because when verstage loads romstage, it overrides it's memory. So pick a different offset for verstage. BUG=b:147042464 TEST=Boot verstage on trembyle and see OS boot. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18soc/intel/tigerlake: Fix wrong operation region for CPU to PCH methodJohn Zhao
CPU to PCH method refers to PCH ACPI operation region which was wrongly defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW method. Change the operation region from SystemIO to SystemMemory to resolve this execution failure. BUG=b:140290596 TEST=Built and booted to kernel. _DSW method executes successfully without ACPI AE_LIMIT error. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-17soc/intel/common: Rename cse_is_hfs3_fw_sku_custom()Sridhar Siricilla
Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU references to CSE Lite SKU. TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-05-17soc/intel/common/block/acpi: Mask lower 20 bits of TOLUDFurquan Shaikh
Lower 20bits of TOLUD register include 19 reserved bits and 1 lock bit. If lock bit is set, then northbridge.asl was reporting the base address of low MMIO incorrectly i.e. off by 1. This resulted in Linux kernel complaining that the MMIO window allocated to the device at the base of low MMIO is incorrect: pci 0000:00:1c.0: can't claim BAR 8 [mem 0x7fc00000-0x7fcfffff]: no compatible brw pci 0000:00:1c.0: [mem 0x7fc00000-0x7fcfffff] clipped to [mem 0x7fc00001-0x7fcfff] pci 0000:00:1c.0: bridge window [mem 0x7fc00001-0x7fcfffff] This change masks the lower 20 bits of TOLUD register when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. TEST=Verified that kernel dmesg no longer complains about the BAR at base of low MMIO. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4849367d5fa03d70c50dc97c7e84454a65d1887a Reviewed-on: https://review.coreboot.org/c/coreboot/+/41455 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-17soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntaxFurquan Shaikh
This change updates northbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-15soc/intel: Correct comment on HMRFPO_ENABLE HECI commandSridhar Siricilla
Correct comment on HMRFPO_ENABLE flow for CSE Lite SKU. In order to place CSE into SECOVER_MEI_MSG mode, below procedure has to be followed. 1. Ensure CSE boots from RO(BP1). - Set CSE's next boot partition to RO - Issue GLOBAL_RESET HECI command to reset the system 2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required. TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I213e02ba3898194fa6c8fe38fab34b5c19f25aa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41340 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14samsung/exynos5420: add resources during read_resources()Furquan Shaikh
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I49ce6ac88c4cb7cd05ff9d78133593ce97304596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41374 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14soc/samsung/exynos5250: add resources during read_resources()Furquan Shaikh
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I419be7edf289636b24b9a7d6c390866ade638de3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14soc/nvidia/tegra124: add resources during read_resources()Furquan Shaikh
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources in read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I16f0439679471366723a0084918a20cd95834831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14soc/amd/stoneyridge: add resources during read_resources()Furquan Shaikh
The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I532f508936d5ec154cbcb3538949316ae4851105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()Furquan Shaikh
This change uses cpu_phys_address_size() to calculate the size of high MMIO region instead of a macro for each SoC. This ensures that the entire range above TOUUD that can be addressed by the CPU is used for MMIO above 4G boundary. Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14soc/intel: Always advertise MMIO window above 4G in ACPI tablesFurquan Shaikh
There should be no harm in advertising the MMIO window above 4G in ACPI tables unconditionally. OS can decide whether or not to use the window. This change removes the config option enable_above_4GB_mmio and instead adds the correct MMIO window (above 4G) details to ACPI tables always. Change-Id: Ie728f6ee7f396918e61b29ade862b57dac36cb08 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41276 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4GFurquan Shaikh
This change sets the base for MMIO above 4G to TOUDD. It matches what is used by resource allocator if MMIO resources are allocated above 4G and also matches the expectation in northbridge.asl. This change also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now unused. BUG=b:149186922 TEST=Verified that kernel does not complain about MMIO windows above 4G. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13lib/spd_bin: add get_spd_sn functionJamie Chen
This patch adds the get_spd_sn function. It's for reading SODIMM serial number. In spd_cache implementation it can use to get serial number before reading whole SPD by smbus. BUG=b:146457985 BRANCH=None TEST=Wrote sample code to get the serial number and ran on puff. It can get the serial number correctly. Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40414 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src/mainboard: Remove unused 'include <stdlib.h>'Elyes HAOUAS
Found using following commande: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l ' memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stddef.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\ |MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stdint.h>'Elyes HAOUAS
unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Enable eSPI capability for PicassoFurquan Shaikh
This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables the capability for using eSPI on Picasso. Additionally, it also calls espi_setup() and espi_configure_decodes() if mainboard enables use of eSPI and skips LPC decodes in that case. BUG=b:153675913,b:154445472 Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-13soc/amd/picasso: Use lpc_early_init() from common lpc driverFurquan Shaikh
This change uses lpc_early_init() for enabling and configuring LPC using the common block LPC driver. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I65784b481ae598bf3a85392ae4fe281aac974097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/common/block: Add support for configuring eSPI connection to slaveFurquan Shaikh
This change adds a helper function espi_setup() which allows SoCs to configure connection to slave. Most of the configuration is dependent upon mainboard settings in espi_config done as part of the device tree. The general flow for setup involves the following steps: 1. Set initial configuration (lowest operating frequency and single mode). 2. Perform in-band reset and set initial configuration since the settings would be lost by the reset. 3. Read slave capabilities. 4. Set slave configuration based on mainboard settings. 5. Perform eSPI host controller configuration to match the slave configuration and set polarities for VW interrupts. 6. Perform VW channel setup and deassert PLTRST#. 7. Perform peripheral channel setup. 8. Perform OOB channel setup. 9. Perform flash channel setup. 10. Enable subtractive decoding if requested by mainboard. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I872ec09cd92e9bb53f22e38d2773f3491355279e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41272 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/mediatek: improve ca53 frequency change procedureWeiyi Lu
To change frequency, the SOC PLL team suggests procedure below: First, we need to enable the intermediate clock and switch the ca53 clock source to the intermediate clock. Second, disable the armpll_ll clock output. Third, raise armpll_ll frequency and enable the clock output. The last, switch the ca53 clock source back to armpll_ll and disable the intermediate clock. BUG=b:154451241 BRANCH=jacuzzi TEST=Boots correctly on Jacuzzi. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13Remove new additions of "this file is part of" linesFurquan Shaikh
CB:41194 got rid of "this file is part of" lines. However, there are some changes that landed right around the same time including those lines. This change uses the following command to drop the lines from new files: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic3c1d717416f6b7e946f84748e2b260552c06a1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41342 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Mark FCH MMIO addresses as non-postedRaul E Rangel
Immediately following FSP-S, update the data fabric routing registers to make the region between HPET and LAPIC as non-posted. If AGESA is modified to do this, we can delete data_fabric_util.c. If AGESA is modified to not program the registers, then we can simplify data_fabric_set_mmio_np(). BUG=b:147042464, b:156296146 TEST=boot trembyle Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Add data fabric pci_devsRaul E Rangel
The device ids are already defined in include/device/pci_ids.h as PCI_DEVICE_ID_AMD_FAM17H_DF*. BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic68a1067e5976af972592d7352c40a5c66dbeb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-13soc/amd/picasso: Add data fabric register definitionsRaul E Rangel
These are used to setup the data fabric. Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Delete northbridgeMarshall Dawson
Family 17h devices are designed with a new internal architecture, frequently referred to as the data fabric. Although designed to behave somewhat like the older integrated northbridge designs, the D18Fx definitions are completely new. The previous northbridge.c was copied from stoneyridge which is completely different. Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Extract reset flags from northbridge.hRaul E Rangel
These are not northbridge functions. BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Move ACP register to acp.hRaul E Rangel
This is a device specific register, not a northbridge register. BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b63571e336f541dcb274e4c8c608f6fc59ff42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41263 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Move acpi_fill_mcfgRaul E Rangel
Move this with the other acpi functions. BUG=b:147042464 TEST=build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I24bd5c7d7c90968759ac745012e7bbc47f0ef6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41262 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/common/block/psp: Remove unused northbridge headerRaul E Rangel
BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5df618f69a7dcca47b9733efb3699b37fd171e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41261 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/common/block/spi: Include mmio.h in fch_spi_ctrl.cFurquan Shaikh
fch_spi_ctrl.c uses read*()/write*() functions which are declared in arch/mmio.h. This change includes the file arch/mmio.h in fch_spi_ctrl.c. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6540004512af1f59f5fb300a3a4818b87ad94bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-13soc/amd/common/block/lpc: Add helper function lpc_early_init()Furquan Shaikh
This change adds a helper function lpc_early_init() which does the following things: 1. Enables LPC controller 2. Disables any LPC decodes (These can be set up later by SoC or mainboard as required). 3. Sets SPI base so that MMIO base for SPI and eSPI controllers is initialized. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I016f29339466c3fee92fe9b62a13d72297c29b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/intel/skylake: Add ability to set root port ASPMWim Vervoorn
The default setting of the root port ASPM configuration can be overridden from the device tree by using a non zero value. BUG=N/A TEST=tested on facebook monolith Change-Id: I85c545d5eacb10f43b94228f1caf1163028645e0 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-12soc/intel/tigerlake: Correct IRQ interruptWonkyu Kim
Current Interrupt setting use 2nd parameters as device function number. - Correct as interrupt pin number according to _PRT package format. {Address, pin, Source, Source index} - Use irq number directly rather than irq definition as its number is not for PCI device. The issue found while enabling GBE and GBE interrupt is not working without this change. Reference - ACPI spec 6.2.13 _PRT - FSP reference code: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/ ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/ PeiItssPolicyLibVer2.c - BIOS reference code: https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/ TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl TEST=boot to OS with GBE enabled and check GBE interrupt Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel
pci_domain_set_resources is duplicated in all the SOCs. This change promotes the duplicated function. Picasso was adding it again in the northbridge patch. I decided to promote the function instead of duplicating it. BUG=b:147042464 TEST=Build and boot trembyle. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/intel/jasperlake: Remove deprecated UPDsRonak Kanabar
IedSize and EnableC6Dram are removed in JSL FSP v2114 so remove them from 'fsp_params.c'. BUG=155054804 BRANCH=None TEST=Build and boot JSLRVP Change-Id: I47bd3f87bdb59625098c0d734695f02d738f8bbd Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41239 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/intel/jasperlake: Add SATA related UPDs configurationRonak Kanabar
This patch control SATA related UPDs based on the devicetree configuration as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-12soc/amd/common/block/lpc: Configure io/mmio windows differently for LPC and eSPIFurquan Shaikh
This change updates lpc_enable_children_resources() to configure IO and MMIO resources differently depending upon whether the mainboard wants to setup decode windows for LPC or eSPI. BUG=b:154445472,b:153675913 Change-Id: Ie8803e934f39388aeb6e3cbd7157664cb357ab23 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/amd/common/block/lpc: Provide an option to use static eSPI BARFurquan Shaikh
This change provides a helper function espi_update_static_bar() that informs the eSPI common driver about the static BAR to use for eSPI controller instead of reading the SPIBASE. This is required to support the case of verstage running on PSP. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1f11bb2e29ea0acd71ba6984e42573cfe914e5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha
FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12soc/amd/common/block/lpc: Add helpers for managing eSPI decodeFurquan Shaikh
This change adds the following helper functions for eSPI decode: 1. espi_open_io_window() - Open generic IO window decoded by eSPI 2. espi_open_mmio_window() - Open generic MMIO window decoded by eSPI 3. espi_configure_decodes() - Configures standard and generic I/O windows using the espi configuration provided by mainboard in device tree. BUG=b:153675913,b:154445472 Change-Id: Idb49ef0477280eb46ecad65131d4cd7357618941 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41073 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/amd/common/block: Add header file for eSPI register definitionsFurquan Shaikh
This change adds eSPI register definitions for I/O and MMIO decode using eSPI on AMD SoCs. Additionally, it also adds a macro to define the offset of ESPI MMIO base from SPI MMIO base. BUG=b:153675913 Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/amd/common/block/lpc: Set LPC_IO_PORT_DECODE_ENABLE to 0 when disabling ↵Furquan Shaikh
decodes This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of lpc_disable_decodes() to ensure that the I/O port decodes are also disabled. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/amd/picasso: Use SPI configuration support from common block SPI driverFurquan Shaikh
This change switches to using the common block SPI driver for performing early SPI initialization and for re-configuring SPI speed and mode after FSP-S has run. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia3186ce59b66c2f44522a94fa52659b4942649b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 07:32:23 +0000