coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-10-18	cpu/amd: Use common AMD's MSR	Elyes HAOUAS
2018-10-18	soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIG	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double definition for wideio	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove DEV_D18F4 definition	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double defined GPIO MMIO bases	Richard Spiegel
2018-10-18	amd/stoneyridge/include/soc: Re-arrange NB IOAPIC definitions	Richard Spiegel
2018-10-18	soc/amd/stoneyridge/smi.c: Prefer using '"%s...", __func__'	Richard Spiegel
2018-10-18	soc/amd/stoneyridge/southbridge.c: Change comparison order	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove "else" after a return	Richard Spiegel
2018-10-18	intel/common/block: Fix issue found by klockwork	John Zhao
2018-10-18	soc/intel/skylake: Prevent disabling of TCO	Naresh G Solanki
2018-10-17	soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions	praveen hodagatta pranesh
2018-10-17	soc/intel/cannonlake: Add new cannon lake PCH-H support	praveen hodagatta pranesh
2018-10-17	mediatek/mt8183: Add USB support	Jumin Li
2018-10-17	mediatek: Refactor USB code among similar SoCs	Tristan Shieh
2018-10-17	soc/cavium/cn81xx: Drop dead do_soft_reset() implementation	Nico Huber
2018-10-14	soc/amd/stoneyridge: Define PM USB Enable register	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Remove hudson EHCI debug controllers	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Rearrange southbridge.h more	Marshall Dawson
2018-10-12	drivers/intel/fsp2_0: Hook up IntelFSP repo	Patrick Georgi
2018-10-12	amd/stoneyridge: Fix PmControl register size in SMI handler	Marshall Dawson
2018-10-12	amd/stoneyridge: Rename CGPLL_CONFIG definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Rename GppClkCntrl fields	Marshall Dawson
2018-10-12	amd/stoneyridge: Rearrange southbridge.h	Marshall Dawson
2018-10-12	amd/stoneyridge: Remove dead GPIO definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Clarify XHCI_PM register definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Fix SPI_CMD_TRIGGER coding style	Marshall Dawson
2018-10-12	amd/stoneyridge: Convert hex definitions to lower case	Marshall Dawson
2018-10-12	amd/stoneyridge: Remove hudson register definitions	Marshall Dawson
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-10-11	src: Replace MSR addresses with macros	Elyes HAOUAS
2018-10-11	amd/stoneyridge: Indicate STAPM units in their name	Richard Spiegel
2018-10-11	selfboot: remove bounce buffers	Ronald G. Minnich
2018-10-11	tegra124_lp0: make sure to build with compiler.h included	Patrick Georgi
2018-10-11	soc/intel/common/block/gpio: check for NULL using if statement	Bora Guvendik
2018-10-10	soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled	Furquan Shaikh
2018-10-10	soc/cavium: dynamic UART initialization for cavium cn8100	Jens Drenhaus
2018-10-10	soc/amd/stoneyridge/gpio.c: Create I2C slave reset code	Richard Spiegel
2018-10-10	mediatek/mt8183: Init PLLs for DRAM	Tristan Shieh
2018-10-09	soc/intel/cannonlake: Add PCIE ASL entry	Subrata Banik
2018-10-09	soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices	Subrata Banik
2018-10-09	soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS i...	Subrata Banik
2018-10-09	soc/intel/common/block/pcr: Add NULL pointer check in pcr_execute_sideband_msg()	Subrata Banik
2018-10-09	soc/intel/cannonlake: Disable Legacy PME for Root ports	Subrata Banik
2018-10-09	soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers	Subrata Banik
2018-10-09	soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers	Subrata Banik
2018-10-09	soc/intel/common/pch: Select Kconfig for ITSS polarity configuration	Subrata Banik
2018-10-08	Move compiler.h to commonlib	Nico Huber