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AgeCommit message (Expand)Author
2020-09-08soc/intel/apollolake: Select CPU_INTEL_COMMONAngel Pons
2020-09-08soc/intel/broadwell: Drop `gpu_panel_port_select`Angel Pons
2020-09-08soc/intel/tigerlake: Add SMRR Locking supportTim Wawrzynczak
2020-09-08soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAPTim Wawrzynczak
2020-09-08soc/mediatek/mt8192: Add SPI flash controller DMA read functionCK Hu
2020-09-06soc/intel/apl: Add panel power and backlight configurationNico Huber
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
2020-09-05soc/intel/alderlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
2020-09-04soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select CPU_INTEL_CO...Elyes HAOUAS
2020-09-04soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer
2020-09-04soc/intel/tigerlake: Remove unused PID_SDX macroSubrata Banik
2020-09-03soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.Jason Glenesk
2020-09-03soc/amd/picasso: Set max_speed_mts and configured_speed_mtsRob Barnes
2020-09-03soc/intel/cnl: Allow using the remaining Comet Lake FSPsFelix Singer
2020-09-033rdparty/fsp: Update submodule pointer to current masterFelix Singer
2020-09-03soc/intel/cnl: Add new Kconfig option which matches its FSPs nameFelix Singer
2020-09-03soc/amd/picasso: Only build PSP bootloader & verstage into ROMartin Roth
2020-09-03soc/amd/picasso: Add config for PSP verstage signing tokenMartin Roth
2020-09-03soc/amd/picasso: Allow use of pre-built PSP verstageMartin Roth
2020-09-03soc/amd/picasso: Move DRAM end to after transfer bufferJosie Nordrum
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
2020-09-02soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'Elyes HAOUAS
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
2020-08-31soc/intel/elkhartlake/romstage: Do initial SoC commit till romstageTan, Lean Sheng
2020-08-31soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblockTan, Lean Sheng
2020-08-31soc/amd/picasso/southbridge: make GPP clock outputs configurableFelix Held
2020-08-31soc/amd/picasso/southbridge.h: rename GPP clock setting offsetsFelix Held
2020-08-31soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macrosFelix Held
2020-08-31soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitionsFelix Held
2020-08-31{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' fileElyes HAOUAS
2020-08-29PCI IDs: Add PCI ID for CML DPTF/DTT PCI deviceEdward O'Callaghan
2020-08-28amd/picasso/psp_verstage: add vboot rsa functionKangheui Won
2020-08-28soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabledMatt Papageorge
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
2020-08-28soc/intel/tigerlake: add ddr4-spd-empty.hexAaron Durbin
2020-08-28mb/google/zork: Switch zork to use spd_toolsRob Barnes
2020-08-28util: Add memory parts needed by zork boardsRob Barnes
2020-08-28util/gen_spd: translate DeviceBusWidth to die bus widthNick Vaccaro
2020-08-28soc/mediatek/mt8192: Use SPI-NOR as flash controllerCK Hu
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
2020-08-27symbols: Change implementation details of DECLARE_OPTIONAL_REGION()Julius Werner
2020-08-27soc/intel/common: Include Elkhart Lake SA IDsTan, Lean Sheng
2020-08-27soc/intel/common: Add Elkhart Lake B0 CPU IDTan, Lean Sheng
2020-08-26soc/mediatek: Include addressmap.h in gpio_common.hCK Hu
2020-08-26soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov
2020-08-25util: Add spd_tools to generate DDR4 SPDs for TGL boardsNick Vaccaro
2020-08-25soc/amd/picasso: If psp_verstage is in RO, don't reset on errorMartin Roth