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2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09soc/intel/skylake: config ISH in SOC sideli feng
Config ISH in SOC side by checking if ISH device is turned on. "IshEnable" is not needed anymore since ISH device on/off will tell if ISH should be enabled or not. "IshEnable" will be removed from chip.h in separate CL. Atlas board specific ISH setting is needed, which is committed in separate CL. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-03soc/amd/stoneyridge: correct GPIO emission error in ACPIKevin Chiu
It can not emit byte data without BytePrefix. design to: Or (Local5, GPIO_PIN_OUT, Local5) error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means nothing in AML spec. so it will include next emitted string in Or: Or (Local5, Local5, \_SB.GPW2) fix: Store (0x40, Local0) Or (Local5, Local0, Local5) BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot extract SSDT then check ACPI syntax is correct Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable legacy IORaul E Rangel
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable IO CF9 in bootblockRaul E Rangel
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mediatek/mt8183: Add mtcmos init supportTristan Shieh
Using common mtcmos code to power on audio and display modules in SOC. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Passes the status check at the end of mtcmos_power_on() Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-02mediatek: Move mtcmos code to a common directoryTristan Shieh
Move mtcmos code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I92b138890424b4f4a68cdb00bf2326eef9cd87b7 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27029 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mediatek: Share mtcmos code among similar SOCsTristan Shieh
Refactor mtcmos code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-02soc/amd/common: Change create_struct return valueKyösti Mälkki
Old return value was not used, and function body has die() in case of errors in allocation. Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e9585187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02soc/amd/common: Fix agesawrapper CreateStruct callsKyösti Mälkki
When AllocationMethod == ByHost, buffer has to be provided by caller. Improve code symmetry, the named parameter is now always pointer to the struct. Change-Id: I2085f7d5d63ef96f4bd9d5194af099634c402820 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-30soc/intel/skylake: Generate ACPI RMRR tableMatt DeVillier
An ACPI RMRR table is requried for IOMMU to work properly with an iGPU (without using passthrough mode), so create one along with the DRHD DMAR table if the iGPU is present and enabled. Test: build/boot google/chell and purism/librem13v2 with kernel parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated graphics functional without corruption. Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29soc/intel/baytrail: Fix Kconfig for mrc.bin inclusionArthur Heymans
It used the sandybridge systemagent binary and mentioned that in the help text which is simply wrong and won't work. This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by default. Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27140 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28amd/common/pi: Remove AGESA support files from bootblockMarshall Dawson
The stoneyridge bootblock no longer makes AGESA calls. Remove the support files from the bootblock build. TEST=boot Grunt Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28amd/common/pi: Remove obsolete heapmanager workaroundMarshall Dawson
Remove residual code that allowed successful building of the heapmanager code. Now that stoneyridge no longer makes AGESA calls in bootblock, it is safe to elimate the workaround. BUG=b:74518368 TEST=boot Grunt Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28fsp_broadwell_de: Add ability to set PCIe completion timeoutDavid Hendricks
This enables the user to set the completion timeout value in PCI Express Device Control 2 register via devicetree.cb. Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release. Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/26225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-06-28soc/intel/skylake: clear MCA before booting to OSPratik Prajapati
mca_configure needs to be called for each core before booting to OS, else OS would keep dumping MCEs Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28intel/common: change mca_configure API's defPratik Prajapati
add an unused param so that mca_configure can be called by mp_run_on_all_cpus to run it on all cores. Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28mediatek/mt8183: Remove the stub flash driver that planned to use eMMCTristan Shieh
The stub flash driver is a temporary hack that planned to adapt eMMC to SPI flash. Remove the hack since SPI flash is what we really expect. BUG=b:80501386 BRANCH=none TEST=Boots fine on Kukui Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-28soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-28soc/intel/apollolake: Remove dead filesFurquan Shaikh
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel Platforms) moved APL to use common SMM code. However, smi.c and smm.h files under soc/intel/apollolake/ were not removed. This change removes the dead files since they are not used anymore. BUG=b:110836465 Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/common: Disable GPEs just before enabling SMIsFurquan Shaikh
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure that we do not end up in a recursive SMI handler loop as mentioned in change 74145f7 (intel/common/pmc: Disable all GPEs during pmc_init). Thus, this call was added at the end of pmc_fill_power_state as we want to ensure that all the GPE registers are backed up before being cleared for identifying the wake source in ramstage. This resulted in a side-effect on APL where pmc_fixup_power_state was called much later in the boot process. Even though we have got rid of pmc_fixup_power_state, this change moves the call to pmc_disable_all_gpe to happen just before enabling SMIs. This helps to keep the disabling of GPEs logically before the enabling of SMIs and any clean ups that happen in pmc or soc-specific code should not affect the state of GPEs. BUG=b:110836465 TEST=Verified that wake sources are correctly identified on KBL and APL. Also, no SMI handler issues observed when resuming. Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/common/block/pmc: Get rid of pmc_fixup_power_stateFurquan Shaikh
Now that APL does not need pmc_fixup_power_state, this function can be removed from the PMC common code as well. BUG=b:110836465 Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28soc/intel/apollolake: Remove call to pmc_fixup_power_stateFurquan Shaikh
On APL, call to pmc_fixup_power_state was added because GPE0_EN registers did not have the right bits set on resume from S3 -- this was a result of GPE_CFG registers getting reset to their default state on resume. GPE_CFG registers are programmed as part of pmc_gpe_init which was previously done only in ramstage. However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in bootblock), call to pmc_gpe_init was added to bootblock which means that GPE_CFG registers will have the right state by the time control reaches romstage where pmc_fill_power_state is called. Thus, call to pmc_fixup_power_state is totally redundant and in fact leads to side-effects because of the call to pmc_disable_all_gpe at the end of pmc_fill_power_state. BUG=b:110836465 TEST=Verified on yorp that wake source is correctly identified on resume from S3. Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-27x86/car: Replace reference of copy_and_run locationKyösti Mälkki
For cases with POSTCAR_STAGE=y this reference pulled in the implementation of run_ramstage() which we would not call. Using _program results with the same region being marked as WRPROT-cacheble. Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
2018-06-26soc/intel/apollolake: Enable logging for wake sources in S0ixFurquan Shaikh
This change adds GSMI callback elog_gsmi_cb_platform_log_wake_source to enable wake source logging from S0ix on APL/GLK. Additionally, elog.c is added to smm stage. BUG=b:79449585 TEST=Verified that S0ix entry/exit events are added to eventlog: =========== Power button ============ 59 | 2018-06-25 14:01:11 | S0ix Enter 60 | 2018-06-25 14:01:30 | S0ix Exit 61 | 2018-06-25 14:02:00 | Wake Source | Power Button | 0 =========== Lid open ================ 62 | 2018-06-25 14:02:36 | S0ix Enter 63 | 2018-06-25 14:02:56 | S0ix Exit 64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15 65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65 66 | 2018-06-25 14:03:37 | EC Event | Lid Open =========== Trackpad ================ 67 | 2018-06-25 14:04:20 | S0ix Enter 68 | 2018-06-25 14:04:33 | S0ix Exit 69 | 2018-06-25 14:05:03 | Wake Source | GPE # | 15 70 | 2018-06-25 14:05:08 | Wake Source | GPE # | 66 Change-Id: I005de58c73d00dc9d7e64f1459f6d786792b94db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27234 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26soc/amd/stoneyridge/southbridge.c: Fix get_index_bit limit checkRichard Spiegel
Limit is the maximum number of bits to be tested, however it's being checked against the number of bytes of uint32_t. when it should be number of bits. Create a macro to provide the number of bits, and use it instead of sizeof. BUG=b:75996437 TEST=Add debug messages to see code passing beyond the check, build and boot grunt, check that it passed the limit check, remove debug code. Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720Simon Glass
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25intel/skylake: nhlt: Add capture config for echo ref stream for Max98373 CodecSathyanarayana Nujella
During Speaker playback, quad Channel I/V feedback data is captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data needs to be given as echo ref stream. So, adding stereo capture config to max98373_capture_formats. BUG=b:110074225 TEST='Audio playback and Capture Stereo echo ref data' Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/27182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23soc/intel/cannonlake: Disable UART_DEBUG by defaultSubrata Banik
This patch ensures serial debug is not enabled by default on Cannonlake platform. Change-Id: Id925c8c73971a027e45ea3c61e878f134bc9feff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/27205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-22sdm845: increase SRAM for bootblockT Michael Turney
Bootblock has grown beyond 32K, grow to 40K Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/26760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-22soc/intel/cannonlake: Remove DMA support for PTTSubrata Banik
Alternative buffer communication support for PTT is no longer needed for CNL onwards and coreboot does not need to reserve additional 4KiB memory for PTT support. Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/27176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21soc/intel/apollolake: unify definition for spi base addressBora Guvendik
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like big core in order make common code implementation straightforward. Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/27097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21soc/intel/common: Make infrastructure ready for Intel common stage filesSubrata Banik
Select all Kconfig belongs into Intel SoC Family basecode/stage files and include required headers from include/intelbasecode/ files. BUG=None BRANCH=none TEST=Code is compiling with cannonlake configurations and also booting on cannonlake RVP. Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-21soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmemRichard Spiegel
PM registers used for generating SWS values are being stored in a static variable within southbridge.c. In order to have it available for any source involved in building the platform, move the storage to cbmem, using id CBMEM_ID_POWER_STATE. Also add a variable that informs from which state the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This variable will later be useful in detecting failed S3 resume. BUG=b:80119811 TEST=Add code to print SWS parameters and state it's waking from. Build and boot grunt, suspend and resume, check output for valid values. Remove the print code. Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27109 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resumeCole Nelson
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume. Disable C1E for SKL and KBL. This gives a coherent state before and after S3 resume. TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3 resume with bit [1] set to zero (0x20005d). Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27125 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21soc/amd/common: Always set GetBiosCalloutKyösti Mälkki
The entire StdHeader field is really supposed to be forked from a template for each entry into the AGESA API. Current code assumes only Callout would be relevant, which is not quite the case. Change-Id: I0cc66d01d62fa8dc6bb7c9f9fab6fa4753827554 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-21mediatek/mt8183: Remove DRAM_DMA sectionTristan Shieh
DRAM_DMA section is used for the special SPI NOR controller on legacy SOC. Remove it since no driver need it currently and we don't have the special SPI NOR controller on mt8183. BUG=b:80501386 BRANCH=none TEST=Boots fine on Kukui Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-21mediatek/mt8183: Add watchdog timer supportTristan Shieh
Using common watchdog timer (WDT) code for reset. Set up watchdog timer in mtk_wdt_init() to get reset status and disable auto-reboot. Link common do_hard_reset() to support hard reset. BUG=b:80501386 BRANCH=none TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui. Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mediatek: Move watchdog timer code to a common directoryTristan Shieh
Move watchdog timer (WDT) code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icbeb04f775c3c0fdc18dd198df8591f5c4b6ddce Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27025 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mediatek: Share watchdog timer code among similar SOCsTristan Shieh
Refactor watchdog timer (WDT) code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27024 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-20fsp_broadwell_de: Add uncore ASL in common locationDavid Hendricks
This patch adds a file for uncore ASL code that is common among Broadwell-DE mainboards but is currently copy + pasted in each of their dsdt.asl files. This is only for clean-up purposes. It is unclear if the code itself is really necessary, but until we can do further investigation and testing it will be left in. Change-Id: I188e5e46dfa7c2ed3991fb97f2c1b5e062e2212d Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/27155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-15soc/intel/{glk,apl} and mainboards: Configure LPC_CLKRUN# pin as GPIO for S0ixHannah Williams
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14stoneyridge: Increase SMM stack size to 2KRaul E Rangel
GSMI Set Event Log is taking more than 1K in stack. This causes the stack to overflow into the adjacent stack. This has the side effect of causing any CPU waiting for the SMI handler to complete to crash when the lock is unlocked because the return pointer has been smashed. BUG=b:80539294 TEST=built on grunt and tested by running `halt` from the OS. Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27033 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14soc/intel/{glk,apl}: ensure C1E is disabled after S3 resumeCole Nelson
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume. Disable C1E for GLK as it is for APL. This gives a coherent state before and after S3 resume. TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3 resume with bit [1] set to zero (0x20005d). Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27019 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 20:16:40 +0000