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path: root/src/soc
AgeCommit message (Expand)Author
2014-11-14t124: Clean up display init functionsJimmy Zhang
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
2014-11-13arm: Put assembly functions into separate sectionsJulius Werner
2014-11-13ipq8064: Make timer code compileVadim Bendebury
2014-11-13ipq8064: Configure proper bootblock stack and load addressVadim Bendebury
2014-11-13Use sbl blobs from a private locationVadim Bendebury
2014-11-13ipq806x: Add support for GPIO operationsFurquan Shaikh
2014-11-13tegra124: Add a macro specifically for configuring the I2C controller clocks.Gabe Black
2014-11-13tegra124: Fix some bugs in the clock configuration macros.Gabe Black
2014-11-13t124: Skip PLLP init to 408MHzJimmy Zhang
2014-11-13t124: nyan: Enable lock bit on pllJimmy Zhang
2014-11-13tegra124: fix OSC initialization on LP0 resumeAndrew Bresticker
2014-11-13tegra124: fix PLLU parametersAndrew Bresticker
2014-11-13tegra124: Make the PLLX frequency selectable by model.Gabe Black
2014-11-12ipq806x: Typecast address to void * in read/write operationsFurquan Shaikh
2014-11-12ipq806x: Add an include/ folder to ipq806xFurquan Shaikh
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
2014-11-12Include IPQ8064 SBLs code in the coreboot bootblockVadim Bendebury
2014-11-12tegra124: enable JTAG in Security ModeJimmy Zhang
2014-11-12tegra124: Program PWM1 to drive panel backlightAndrew Chew
2014-11-12tegra124: Add pwm_controller registersAndrew Chew
2014-11-12tegra124: Fix PWM pinmux functionsAndrew Chew
2014-11-12tegra124: Add PWM base addressAndrew Chew
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
2014-11-09Provide ability to integrate with QComm SBLsVadim Bendebury
2014-11-09arm: Thumb ALL the things!Julius Werner
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
2014-10-22tegra/nyan*: sdram updatesTom Warren
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
2014-10-22broadwell: Update microcodeDuncan Laurie
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
2014-10-22broadwell: add new intel SOCDuncan Laurie
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
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