coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-11-22	Create SOC description file soc.asl	Richard Spiegel
2017-11-21	src/soc/intel/apollolake: move TCO1 disable into bootblock	Vadim Bendebury
2017-11-21	soc/amd/stoneyridge: Add ELOG to SMM	John E. Kabat Jr
2017-11-21	amd/stoneyridge/spi: Fix reads greater than 5 bytes	Marshall Dawson
2017-11-21	soc/amd/common: Remove duplicated #include amd_pci_int_defs.h	Richard Spiegel
2017-11-20	soc/intel/cannonlake: Add ACPI workaround for EMMC	Lijian Zhao
2017-11-20	amd/stoneyridge: Fix SPD files and functions camel case	Marc Jones
2017-11-17	Move amd/stoneyridge/include/amd_pci_int_defs.h to include/soc/	Richard Spiegel
2017-11-17	soc/intel/cannonlake: fix gpio pin numbers	Bora Guvendik
2017-11-17	soc/intel/cannonlake: Add cpu.asl file	Shaunak Saha
2017-11-17	amd/stoneyridge: Enable SMI trap on SlpTyp	Marshall Dawson
2017-11-17	amd/stoneyridge: Add SlpTyp SMI handler	Marshall Dawson
2017-11-17	amd/stoneyridge: Add SPI controller driver	Marshall Dawson
2017-11-16	vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.h	Martin Roth
2017-11-15	mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc	Richard Spiegel
2017-11-15	soc/intel/skylake: Make use of common CSE code for skylake	Subrata Banik
2017-11-15	soc/intel/common: Use HOST_CSR to get circular Buffer Depth	Subrata Banik
2017-11-15	soc/intel/common: Add HECI message retry count	Subrata Banik
2017-11-15	soc/intel: Enable ACPI DBG2 table generation	Duncan Laurie
2017-11-15	soc/intel/cannonlake: Fix and clean up xhci ACPI code	Vaibhav Shankar
2017-11-14	soc/amd/stoneyridge: Remove direct AGESA header includes	Martin Roth
2017-11-14	soc/amd/common: Remove direct AGESA header includes	Martin Roth
2017-11-14	AMD Stoney Ridge: Add agesa_headers.h	Martin Roth
2017-11-14	amd/common/spi: Update flash driver usage	Marshall Dawson
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-14	amd/stoneyridge: Add generic IMC sleep and wakeup	Marshall Dawson
2017-11-14	amd/stoneyridge: Replace BIT(n) in southbridge	Marshall Dawson
2017-11-14	amd/stoneyridge: Define bits for AcpiConfig	Marshall Dawson
2017-11-13	soc/intel/common: Add error print in common i2c	Lijian Zhao
2017-11-13	soc/intel/cannonlake: Define default LPSS clock	Lijian Zhao
2017-11-13	soc/amd/stoneyridge: Add CPU PPKG ASL	Marc Jones
2017-11-13	soc/amd/stoneyridge: Add GNVS variables for thermal control	Marc Jones
2017-11-13	soc/amd/stoneyridge: Fix DRAM clear check	Marshall Dawson
2017-11-11	soc/intel/apollolake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/apollolake: Add support for SPI device	Subrata Banik
2017-11-11	soc/intel/cannonlake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/skylake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routine	Subrata Banik
2017-11-11	soc/intel/common/block: Add Intel common SPI support	Subrata Banik
2017-11-10	soc/amd/stoneyridge: Add UMA settings to devicetree	Aaron Durbin
2017-11-10	amd/stoneyridge: Implement vboot_platform_is_resuming	Marshall Dawson
2017-11-10	amd/stoneyridge: Add function to find Pm1EvtBlk base	Marshall Dawson
2017-11-10	amd/stoneyridge: Remove dead southbridge definitions	Marshall Dawson
2017-11-10	amd/stoneyridge: Add more ACPI register definitions	Marshall Dawson
2017-11-10	amd/stoneyridge: Use the new generic acpi_sleep_from_pm1	Marshall Dawson
2017-11-10	amd/stoneyridge: Select AMD common sleep states	Marshall Dawson
2017-11-10	soc/amd/stoneyridge: Use uint8_t as type for SPD address	Richard Spiegel
2017-11-10	soc/amd/stoneyridge: Simplify and fix SMBUS code	Richard Spiegel
2017-11-10	soc/amd/common: Add DRAM clear option to northbridge.c	Richard Spiegel
2017-11-10	soc/intel/cannonlake: Remove structure variable initialization with 0	Subrata Banik