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2020-03-26soc/intel/xeon_sp: Configure P2SB BAR in bootblockAndrey Petrov
In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-26soc/intel/xeon_sp: Refactor code to allow for additional CPUs typesAndrey Petrov
Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25create stdio.h and stdarg.h for {,v}snprintfJoel Kitching
Sometimes coreboot needs to compile external code (e.g. vboot_reference) using its own set of system header files. When these headers don't line up with C Standard Library, it causes problems. Create stdio.h and stdarg.h header files. Relocate snprintf into stdio.h and vsnprintf into stdarg.h from string.h. Chain include these header files from string.h, since coreboot doesn't care so much about the legacy POSIX location of these functions. Also move va_* definitions from vtxprintf.h into stdarg.h where they belong (in POSIX). Just use our own definitions regardless of GCC or LLVM. Add string.h header to a few C files which should have had it in the first place. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-25amd/common/acpi: move thermal zone to common locationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25soc/intel/cometlake: Use IntelFSP repoFelix Singer
Make use of the publicly-available FSP binaries and headers for Comet Lake. Also, remove the Comet Lake header files from src/vendorcode, since they are no longer necessary. Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25soc/intel/xeon_sp: Enable LPC generic IO decode rangeJohnny Lin
To use Intel common block LPC function that enables the IO ranges defined in devicetree.cb. Tested on OCP Tioga Pass with BMC LPC working. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25soc/intel/tigerlake: Configure HyperthreadingWonkyu Kim
Configure Hyperthreading based on devicetree BUG=none TEST= Build and boot with FSP log and check Hyperthread setting Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24intel/broadwell: Correct backlight-PWM dividerNico Huber
The PWM-granularity chicken bit in the Wildcat Point and Lynx Point PCHs has actually the opposite meaning of the one for Sunrise Point and later. When the bit is set, we get a divider of 16, when it's unset 128. Flip the bit! Change-Id: I1dbde1915d8b269c11643a1636565a560eb07334 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZETim Wawrzynczak
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23soc/intel/braswell: Clean upAngel Pons
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected. Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23soc/intel/cfl/vr_config: Add 8-core desktop CPU supportPatrick Rudolph
Add 8-core desktop CPU support by adding the corresponding PCI IDs. Tested using "Intel Core(TM) i7-9700E". Change-Id: I7a2e2e5fd1796deff81b032450242fb58031526d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-21soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition properSubrata Banik
This patch makes PCH_DEV_UART3 macro referring to _PCH_DEV() rather calling _PCH_DEVFN(). Change-Id: I7bc060c3c5f1e0a0fed194704b4940db73f46985 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20soc/intel: Enable GPIO functions in verstageBora Guvendik
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20soc/intel/denverton_ns: Implement AES-NI LockJulien Viard de Galbert
Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Steve Mooney Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20soc/intel/tigerlake: Enable ACPI support for PMC core OS driverVenkata Krishna Nimmagadda
PMC core driver in OS provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. This patch adds INT33A1, a required ACPI device, to support that PMC core driver in tigerlake platform. BUG=b:146236297 BRANCH=none TEST="Build and flash volteer and verify it boots to kernel. Checked for valid files under /sys/kernel/debug/pmc_core." Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib7e583dc2943461a41d2a7ebde1f16a58a118975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39587 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20soc/intel/common: Add ACPI support for PMC core OS driverVenkata Krishna Nimmagadda
PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. This patch adds INT33A1 ACPI device to support PMC core OS driver. Any SoC that supports this feature would include this asl file to enable the support. BUG=b:146236297 BRANCH=none TEST="Build and flash volteer and verify it boots to kernel" Change-Id: Ib4edc7b636725177d508b62d15633534e9f44236 Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2362512 Reviewed-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.corp-partner.google.com> Commit-Queue: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39370 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19soc/intel/xeon_sp: Modify FSP-T code caching parametersJohnny Lin
Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching parameters. Tested on OCP Tioga Pass. Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39625 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Andrey Petrov <anpetrov@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19soc/intel/tigerlake: add support to read SPD data from SMBusRonak Kanabar
Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD data. So, add support to read SPD data from SMBUS. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19soc/intel/tigerlake: Update header to avoid compilation issueMaulik V Vaghela
We were including stddefs.h and stdint.h but compilation fails when we use 'bool' type in file. Removing stddef.h and stdint.h and including 'types.h' which includes all data types BUG=None BRANCH=None TEST=Check if compilation passes when bool is used Change-Id: I4c9001f729f3103deba9d1fd631a8942c23276ee Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-18soc/amd/picasso: Add CPUID of newer deviceMarshall Dawson
Add a new device (Family 17h Models 20h-2Fh) to the cpu driver. Change-Id: Id792533e60813b7509bacd6806f78cd8bba56e37 Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1950713 Reviewed-by: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc/intel/tigerlake: Correct number of gpio group for Jasper LakeMaulik V Vaghela
Correct number of gpio pad group for Jasper Lake SoC. BUG=None BRANCH=None Test=Code compilation for Jasper Lake RVP Change-Id: I381d0e48430e933569a3b22b66b4e6077383e9e2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-18soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBTBrandon Breitenstein
FSP needs to know to allow the root ports for USB4/TBT to be enabled This patch may need additional checks for each board as it might not be the right thing to turn them all on for every Tiger Lake board. BUG=b:141609883 BRANCH=NONE TEST=Built image and verified that the root ports were visible with lspci Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-18soc/mediatek/mt8183: Fix wrong setting of DRS configHuayang Duan
Update setting of DRS config. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-18soc/mediatek/mt8183: Improve the AC timing of DRAMCHuayang Duan
Set more AC timing items to make the system more stable. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Ibd003582a3ffab1ae91f6378651c2c9e585c4676 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-18soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini LakeFranklin He
Enables Gaussian Mixture Model (GMM) if the pci device is enabled in the devicetree for Gemini Lake This ports commit 03ddd190fd6a2e91b16e6fd8a101cf4e11d7cd7b BUG=b:151115705 BRANCH=none TEST=Flashed to Chromebook, PCI device enabled in cbmem, userspace app that uses device still works Change-Id: I72b1dd78705894f0462c7fbe89b76551950c2392 Signed-off-by: Franklin He <franklinh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-18soc/intel/skylake: Control fixed IO decode from devicetreeWim Vervoorn
The current implementation doesn't allow custom values for the LPC IO decodes and IO enables. Add the lpc_ioe and lpc_iod values. If they are not zero, they will be used instead of the current handling for COMA and COMB. BUG=N/A TEST=tested on facebook monolith Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38748 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17soc/amd/picasso: Set I2C clock reference to 150MHzMartin Roth
Picasso uses a 150MHz reference clock for the Designware I2C devices. This update allows us to get the correct speeds out. BUG=b:143885765 TEST=Trembyle has 400kHz I2C clock Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1970656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17soc/amd/picasso: Remove unused defines from cpu.hMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4ed3e7c82ef5808a0e96c07c16f4872f8ca3ec76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17soc/amd/picasso: Move get_soc_config to common locationMarshall Dawson
Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASLRizwan Qureshi
Method RAOW is assuming that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sending the exact address of the register to be updated. Also MCCT was setting the clock frequency in both case i.e, Clock Enable and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing like below MCON: Set frequency Enable clock MCOF: Disable clock Also, make use of MCON and MCOF methods for camera clock control in tglrvp. This is to avoid the buildbot marking the patch unstable. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17soc/intel/cannonlake: Set correct serirq modeJeremy Soller
Set FSP params PchSirqEnable/PchSirqMode based on board setting of serirq_mode. Matches implementation on Skylake. This is a no-change for existing boards since the default remains SERIRQ_QUIET mode. Tested on system76 galp3-c, out-of-tree WHL-U board Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nathaniel L Desimone <nathaniel.l.desimone@intel.com>
2020-03-17soc/broadwell: remove unused function init_one_gpio()Matt DeVillier
Function was copied as part of upstreaming from Chromium tree, but isn't used and has never been used best I can tell. Change-Id: I53b8702c97d7a694450aa05ba49da6c26c30f725 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-16soc/intel/tigerlake: Support ISHli feng
Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-16src/soc/tigerlake_dev: Update PMC IPC Hardware IDJohn Zhao
Change PMC IPC HID from INT34D2 to INTC1026 along with new kernel pmc ipc driver. BUG=b:148949891 BRANCH=none TEST=Boot on Volteer and validate DP tunneling. Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-15soc/intel/Kconfig: Avoid specifying dedicated chipset nameSubrata Banik
This patch ensures all IA chipsets and common Kconfig files are getting included without specifying dedicated chipset names. TEST=Able to compile CML and TGL RVP. Change-Id: Ic2d8a8ac1c4acfabd4ded1bfd4ff359e820e174b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39530 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15soc/intel/common: Check prerequisites for GLOBAL_RESET commandSridhar Siricilla
Check prerequisites before sending GLOBAL RESET command to CSE. TEST=Verified on hatch. Change-Id: Ia583e4033f15ec20e942202fa78e7884cf370ce4 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE commandSridhar Siricilla
Below changes are done: 1. Allow execution of HMRFPO_ENABLE command if CSE meets below prerequisites: - Current operation mode(COM) is Normal and Curret working state(CWS) is Normal. -(or) COM is Soft Temp Disable and CWS is Normal if ME's Firmware SKU is Custom. 2. Check response status. 3. Add documentation for send_hmrfpo_enable_msg(). 4. Rename padding field of hmrfpo_enable_resp to reserved. The HMRFPO (Host ME Region Flash Protection Override) mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perform updates to it. This command is only valid before EOP(End of Post). For Custom SKU, follow below procedure to place CSE in HMRFPO mode: 1. Ensure CSE boots from BP1. When CSE boots from BP1, it will have opmode Temp Disable Mode. 2. Send HMRFPO_ENABLE command to CSE. Then, CSE enters HMRFPO mode. CSE Firmware Custom SKU Image Layout: = [RO] + [RW + DATA PART] = [BP1] + [BP2 + DATA PART] Here, BP1 will have reduced functionality of BP2, and the BP1 will be CSE's RO partition and [BP2 + DATA PART] together will represent CSE's RW partition. CSE can boot from either BP1(RO) or BP2(RW). CSE Image Layout in Consumer SKU: BP2 + BP3 + DATA PART TEST=Verfied on hatch board. Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15soc/intel/icelake: Re-flow comment for 96 charactersPaul Menzel
Change-Id: I7a5d7bb476c33ab995136eb47ef0258b483a42ef Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15soc/intel/icelake: Correct past participle in commentPaul Menzel
Change-Id: I117c8d2f71824292c4ca87b6f9434d2106bb512d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15soc/intel/tigerlake: Match RP number with TGL EDSWonkyu Kim
Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2. BUG=b:151208838 TEST=build RVP successfully Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-03-15soc/intel/tigerlake: Enable CNVi through dev_enabledSrinidhi N Kaushik
Check for dev enabled status for CNVi and update the UPD accordingly. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-15soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik
Add config to override CpuRatio or setting CpuRatio to allowed maximum processor non-turbo ratio. BUG=151175469 BRANCH=none TEST=Build and boot tglrvp and observe there is no extra reset in meminit. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15soc/intel/tigerlake: Configure Vmx support using KconfigJohn Zhao
Change VmxEnable UPD value based on Kconfig ENABLE_VMX BUG=None TEST=Built image and booted to kernel. Change-Id: I725474643193223865a135813cf882fd7636d24a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-12soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI tableJohn Zhao
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-12soc/intel/*/smihandler: Only compile in TCO SMI handler if neededPatrick Georgi
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case. Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2020-03-12soc/intel/tigerlake: Configure L1Substates for PCH Root portsWonkyu Kim
Set value for PcieRpL1Substates according to devicetree. Chip config parameter PcieRpL1Substates uses (UPD value + 1) because UPD value of 0 for PcieRpL1Substates means disabled for FSP. In order to ensure that mainboard setting does not disable L1 substates incorrectly, chip config parameter values are offset by 1 with 0 meaning use FSP UPD default. get_l1_substate_control() ensures that the right UPD value is set in fsp_params. Chip config parameter values 0: Use FSP UPD default 1: Disable L1 substates 2: Use L1.1 3: Use L1.2 (FSP UPD default) BUG=none BRANCH=none TEST=Boot up and check FSP log for PCIe config for this values Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 08:48:14 +0000