summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Expand)Author
2020-07-28src: Never set ISA Enable on PCI bridgesAngel Pons
2020-07-28soc/intel/braswell/fadt.c: Use `ACPI_ADDRESS_SPACE_IO` macroAngel Pons
2020-07-28broadwell: Factor out PIRQ routing from devicetreeAngel Pons
2020-07-28soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabledFelix Singer
2020-07-28soc/intel/apollolake: Simplify is-device-enabled checksFelix Singer
2020-07-28soc/intel/jasperlake: Simplify is-device-enabled checksFelix Singer
2020-07-28soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer
2020-07-28Revert "src: Remove unused include <cpu/x86/smm.h>"Patrick Rudolph
2020-07-27soc/amd: Use spi_writeX & spi_readX for all spi accessesMartin Roth
2020-07-27soc/amd/common: Move spi access functions into their own fileMartin Roth
2020-07-27soc/amd/picasso: Set __USER_SPACE__ for psp_verstageMartin Roth
2020-07-27soc/amd/picasso: make USB over-current pin mapping configurableFelix Held
2020-07-27soc/intel/jasperlake: Invoke PCIe root port swappingKarthikeyan Ramasubramanian
2020-07-26soc/intel/tigerlake: Disable CPU PCIe in FSPShaunak Saha
2020-07-26soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platformJohn Zhao
2020-07-26soc/intel/common/basecode: Implement CSE update flowRizwan Qureshi
2020-07-26soc/amd/common/block/psp/psp_smm.c: Add missing <string.h>Elyes HAOUAS
2020-07-26src/soc/qualcomm: Add include <types.h>Elyes HAOUAS
2020-07-26src/soc/mediatek: Add include <types.h>Elyes HAOUAS
2020-07-26src/soc/intel: Add include <types.h>Elyes HAOUAS
2020-07-26soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIGMaxim Polyakov
2020-07-26soc/intel/common/hda: Add HDA ID for Jasper Lakeyan.liu
2020-07-26soc/intel/jasperlakelake: Rename pch_init() codeUsha P
2020-07-26src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
2020-07-26src: Remove whitespace between 'sizeof' and '('Elyes HAOUAS
2020-07-26{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bitsAngel Pons
2020-07-26soc/amd/common: Refactor and consolidate code for spi baseMartin Roth
2020-07-26soc/amd/picasso: Update postcode valueMartin Roth
2020-07-26Kconfig: Remove unnecessary choice namesMartin Roth
2020-07-26smp/spinlock: Do not define barrier() globallyKyösti Mälkki
2020-07-26arch/x86: Move cpu_relax()Kyösti Mälkki
2020-07-26cpu,soc/intel: Drop select SMPKyösti Mälkki
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
2020-07-26skylake boards: Factor out copy-pasted PIRQ routesAngel Pons
2020-07-26src: Remove unused include <cpu/x86/smm.h>Elyes HAOUAS
2020-07-26amd/picasso: rework USB2 PHY tune parameter handlingFelix Held
2020-07-26soc/skylake: Configure SATA options only if SATA is enabledFelix Singer
2020-07-25soc/amd/picasso: don't apply unconfigured USB2 PHY tune parametersFelix Held
2020-07-25soc/intel/baytrail/southcluster.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/include/soc/irq.h: Add bracesAngel Pons
2020-07-25soc/intel/baytrail: Simplify pattrs definitionsAngel Pons
2020-07-25soc/intel/baytrail/smm.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/smihandler.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/cpu.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/sd.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/lpss.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/lpe.c: Align with BraswellAngel Pons
2020-07-25soc/intel/{baytrail,braswell}: Drop unneeded `return`Angel Pons