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2020-09-09soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbolAngel Pons
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332Subrata Banik
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-08pci_ids: Add Alder Lake DTT PCI IDsSubrata Banik
Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45140 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08pci_ids: Add Alder Lake IPU PCI IDsSubrata Banik
Add PCI IDs for Intel's Image Processing Unit (IPU) for ADL. Also add NULL terminator at end of pci_device_ids. Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/mediatek/mt8192: Add SPI flash controller dual read functionCK Hu
Support SPI flash dual read funciton which change spi mode (1-1-1) to dual mode (1-1-2). Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44852 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/baytrail: Add missing GSM size definitionsAngel Pons
Change-Id: I456591f63f463c5cec1cbf3c1633bdb61be92d29 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44935 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE'Elyes HAOUAS
Change-Id: I25cfc61b7a25b68dd22573a88933e03931a755ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian <d.guckian20@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/tigerlake: Skip GPIO configuration from FSPSrinidhi N Kaushik
FSP v3333 or later, provides a new UPD to Skip configuring GPIO settings from FSP. coreboot should provide all the required GPIO configuration for the platform when this UPD is set. BUG=b:166790597, b:146390704 BRANCH=none TEST=build and boot volteer proto2 Cq-Depend:chromium-internal:3240396,chromium-internal:2870145 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/elkhartlake: Update SA & PM related definitionsTan, Lean Sheng
1. Update SA base address & size 2. Update GBE control bit register value Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake: Update PMC related register definitionsTan, Lean Sheng
Update ABase, PMC GPIO value sets and PMC register base address. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs TableTan, Lean Sheng
1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c 2. Add additional EHL SA DID in pci_ids.h Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlakeTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Rename from jasperlake to elkhartlake 2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op) Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08soc/intel/elkhartlake: Do initial SoC commit till ramstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jsp" with "mcc" 4. Rename structure based on Jasperlake with Elkhartlake 5. Clean up upd override in fsp_params.c will be added later 6. Sort #include files alphabetically as per comment 7. Remove doc details from espi.c until it is ready 8. Remove pch_isclk & camera clocks related codes 9. Add new #define NMI_STS_CNT & NMI_EN as per comment Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08soc/intel/apollolake: Hook up ENABLE_VMXAngel Pons
Unlike other platforms, Apollo and Gemini Lake have VmxEnable on FSP-S. Note that this will enable VMX by default on both of these platforms. Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-08soc/intel/apollolake: Select CPU_INTEL_COMMONAngel Pons
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems. Tested with BUILD_TIMELESS=1, UP Squared does not change. Gemini Lake already selects this through SOC_INTEL_COMMON_BLOCK_SGX. Change-Id: If737fa6d8700f435c8692c80244f0e71657c2236 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-08soc/intel/broadwell: Drop `gpu_panel_port_select`Angel Pons
The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08soc/intel/tigerlake: Add SMRR Locking supportTim Wawrzynczak
The SMRR MSRs can be locked, so that a further write to them will cause a #GP. This patch adds that functionality, but since the MSR is a core-level register, it must only be done once per core; if the SoC has hyperthreading enabled, then attempting to write the SMRR Lock bit on the primary thread will cause a #GP when the secondary (sibling) thread attempts to also write to this MSR. BUG=b:164489598 TEST=Boot into OS, verify using `iotools rdmsr` that all threads have the Lock bit set. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAPTim Wawrzynczak
The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs can be "locked" and this patch adds the definition for that. BUG=b:164489598 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08soc/mediatek/mt8192: Add SPI flash controller DMA read functionCK Hu
To speed up SPI flash read, enable DMA read function. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Ic1679ef7940258350feeadac50ad8ea407fd7b90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-09-06soc/intel/apl: Add panel power and backlight configurationNico Huber
Change-Id: Id8892ac7aafce1006831e2d9f2806919f5950756 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-06soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner
Fsp configures the USB over-current pin and overrides the according pad configuration to NF1, regardless of the port being configured as disabled. Thus, set the OC pin to 0xff ("disabled") in this case to prevent this. This allows us to skip setting USBx_PORT_EMPTY in the devicetree for disabled USB ports. Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-05soc/intel/alderlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
List of changes: 1. Add required SoC programming till bootblock 2. Include only required headers into include/soc 3. Add CPU/PCH/SA EDS document number and chapter number 4. Include ADL-P related DID, BDF Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I204e692fabb84fce297bebee465f4ca624c6fe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-04soc/intel/{jasperlake,tigerlake}/Kconfig: Drop redundant 'select ↵Elyes HAOUAS
CPU_INTEL_COMMON_SMM' CPU_INTEL_COMMON_SMM is set to yes if CPU_INTEL_COMMON at cpu/intel/common/Kconfig. Change-Id: I7c8e1bb6b7c3199a24711b64a6cbba4de190c6d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-04soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer
Currently HECI3 gets enabled by the option Heci3Enabled, but this duplicates the devicetree on/off options. Therefore depend on the devicetree for enablement of the HECI3 controller. All corresponding mainboards were checked if the devicetree configuration matches the Heci3Enabled setting, and divergent devicetrees were adjusted. Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-04soc/intel/tigerlake: Remove unused PID_SDX macroSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I177a146643f2196018182502fff8d82830e139dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-03soc/amd/picasso/acpi: Remove padding in IVRS table caused by realignment.Jason Glenesk
Previous CL (1916f8969b10e27fe06b3e0eb1caae632bd947f6) misinterpreted spec as requiring size alignment on all IVHD device entries. The correct requirement specifies only for 4-byte entries. The unneeded realignments result in gaps in the table. The kernel hangs in early boot due to the malformed table. Remove 8-byte entry alignment. BUG=b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Confirm IVRS contains no alignment gaps/corruption. Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-03soc/amd/picasso: Set max_speed_mts and configured_speed_mtsRob Barnes
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03soc/intel/cnl: Allow using the remaining Comet Lake FSPsFelix Singer
To allow using the 3 remaining Comet Lake SoCs, add a new Kconfig option for each of them and configure the paths to FSP header files and FSP binary. Change-Id: I4272a6ee08e19769a8a17c93bb3ce2421be0bbc9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Michael Niewöhner
2020-09-033rdparty/fsp: Update submodule pointer to current masterFelix Singer
Change-Id: I50bac5a70425495832649e0d6d6e91aad623f25c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03soc/intel/cnl: Add new Kconfig option which matches its FSPs nameFelix Singer
Since there are 4 different versions of FSPs for the Comet Lake platform, add a new Kconfig option for the currently used SoC being able to differ between the various SoCs and FSPs. The new Kconfig option selects the Comet Lake SoC as base for taking over its specific configuration and is only used for configuring the path to its specific FSP header files and FSP binary. Also, adjust all related mainboards so that their Kconfig selects the new option. For details, please see https://github.com/intel/FSP/tree/master/CometLakeFspBinPkg Built System76/lemp9 with BUILD_TIMELESS=1 before and after this patch and both images are equal. Change-Id: I44b717bb942fbcd359c7a06ef1a0ef4306697f64 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-03soc/amd/picasso: Only build PSP bootloader & verstage into ROMartin Roth
The PSP bootloader and verstage are only used out of the RO region, so don't build them into the RW sections. BUG=None TEST=Build & Boot BRANCH=zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Add config for PSP verstage signing tokenMartin Roth
This allows a platform to specify the location of the signing token for the PSP verstage, and build it into the firmware image. BUG=b:166108929 TEST=Build file into PSP firmware, verify that it's present and has the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Allow use of pre-built PSP verstageMartin Roth
To use a signed PSP verstage, we're going to need to build it first, then sign and store the binary. This patch allows the stored (signed) verstage binary to be used. BUG=b:166108929 TEST=Build with existing verstage binary instead of re-building it. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-03soc/amd/picasso: Move DRAM end to after transfer bufferJosie Nordrum
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the transfer buffer actually lives within the 32KiB that is supported to be transferred. Resulting symbol address change in bootblock.debug file summarized below. BEFORE: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02019000 T _epsp_sharedmem_dram 02019000 T _preram_cbmem_console 0201a600 T _epreram_cbmem_console 0201a600 T _timestamp 0201a800 T _etimestamp 0201a800 T _fmap_cache 0201ac52 T _efmap_cache 0201ac52 T _etransfer_buffer AFTER: 02011000 T _psp_sharedmem_dram 02011000 T _transfer_buffer 02011000 T _transfer_info 02011040 T _etransfer_info 02011040 T _vboot2_work 02014040 T _evboot2_work 02014040 T _preram_cbmem_console 02015640 T _epreram_cbmem_console 02015640 T _timestamp 02015840 T _etimestamp 02015840 T _fmap_cache 02015c92 T _efmap_cache 02015c92 T _etransfer_buffer 02019000 T _epsp_sharedmem_dram BUG=b:167243965 BRANCH=None TEST=checked 'cbmem -1' for FMAP error after ec reboot Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02soc/intel/tigerlake: Add mainboard hook for overriding SoC configJes Klinke
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Iff28e4a29fab5c22c410cdc743d0402134c4ac56 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'Elyes HAOUAS
POSTCAR_CONSOLE is already set to yes in console/Kconfig file. Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31soc/intel/elkhartlake/romstage: Do initial SoC commit till romstageTan, Lean Sheng
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 4. Clean up upd override in fsp_params.c, will be added later 5. Temporarily remove _weak attributes in fsp_param & romstage.c 6. Add required headers into include/soc/ from jasperlake directory Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-31soc/intel/elkhartlake/bootblock: Do initial SoC commit until bootblockTan, Lean Sheng
Clone entirely from Jasperlake This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/36550 List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Rename structure based on Jasperlake with Elkhartlake 6. Add required headers into include/soc/ from JSL directory Elkhart Lake specific changes will follow in subsequent patches. 1. soc/intel/elkhartlake: Update Kconfig Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-08-31soc/amd/picasso/southbridge: make GPP clock outputs configurableFelix Held
Make the general purpose PCIe clock outputs configurable to be either permanently enabled, permanently disabled or dynamically enabled via their corresponding external #CLK_REQx pins in the board's devicetree. BUG=b:149970243 BRANCH=zork Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: rename GPP clock setting offsetsFelix Held
The _SHIFT postfix is a bit clearer than the _SHL one and more in line with the names used for this kind of defines in coreboot. The documentation on that register is currently wrong and will hopefully be fixed in the future; the defines should now match the hardware. BUG=b:149970243 BRANCH=zork Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: replace GPP_CLK_REQ_MAP_* with macrosFelix Held
Replacing the existing defines with macros makes them easier to use in a function that applies the setting for a certain GPP/GFX clock output. Also add macros for statically enabling or disabling the clock outputs and not only for configuring them as controlled by the #CLK_REQx pins. BUG=b:149970243 BRANCH=zork Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-31soc/amd/picasso/southbridge.h: remove OSCOUT*_CLK_OUTPUT_ENB definitionsFelix Held
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and this was probably just copied over from stoneyridge. BUG=b:149970243 BRANCH=zork Change-Id: I32f459026c4e8632672123681b20736245f198b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31{intel/gma,include/device}: Delete unused 'drm_dp_helper.h' fileElyes HAOUAS
'drm_dp_helper.h' file is duplicated and not used. Change-Id: Ibb08f7ff91c3914940dfe899be331b06e292c7c9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-29PCI IDs: Add PCI ID for CML DPTF/DTT PCI deviceEdward O'Callaghan
This PCI ID is required in order for the CML devices to perform SSDT generation for DPTF. CML Processor, EDS, Vol 1, Table 9-5, Section 9.2. BUG=b:158986928 BRANCH=puff TEST=builds Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Andrew McRae <amcrae@google.com>
2020-08-28amd/picasso/psp_verstage: add vboot rsa functionKangheui Won
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa signature against digest using PSP svc. This function will be later used by vboot to accelerate rsa verification. BUG=b:163710320, b:161205813 TEST=build zork firmware with vboot modification, confirm it's booting and boot time is reduced by ~230ms. Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabledMatt Papageorge
FSP has recently added support for a UPD switch to power gate SATA. This change adds the coreboot side of the feature. To avoid having two SATA enable options, the value of the sata_enable UPD is determined by the enable state of the AHCI controller in the platform devicetree. BUG=b:162302027 BRANCH=zork TEST=Verify AHCI controller can be hidden/disabled. Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 07:40:44 +0000