coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-10-25	soc/intel/cannonlake: Enable S4 sleep state support	praveen hodagatta pranesh
2018-10-25	soc/amd/common/pi: Correct top of DRAM reporting by AGESA	Marshall Dawson
2018-10-24	mediatek/mt8183: Initialize DRAM with a sequence in constant array	Huayang Duan
2018-10-24	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	Joel Kitching
2018-10-23	src: Remove unneeded whitespace	Elyes HAOUAS
2018-10-23	soc/amd/stoneyridge: Remove smbus.asl	Richard Spiegel
2018-10-23	soc/intel/common/block/gpio: Allow GPI to be dual-routed	Furquan Shaikh
2018-10-23	soc/intel/common/block/gpio: Configure Tx Disable in IO standby for GPIs	Furquan Shaikh
2018-10-23	soc/intel/apollolake: Add reset code to postcar stage	Patrick Georgi
2018-10-22	intel: Use CF9 reset (part 2)	Patrick Rudolph
2018-10-22	intel: Use CF9 reset (part 1)	Patrick Rudolph
2018-10-22	soc/amd: Implement common reset API	Nico Huber
2018-10-22	soc/samsung/exynos5250: Convert to `board_reset()`	Nico Huber
2018-10-22	soc/mediatek: Convert to `board_reset()`	Nico Huber
2018-10-22	soc/imgtech/pistachio: Convert to `board_reset()`	Nico Huber
2018-10-22	soc/rockchip/rk3399: Convert to `board_reset()`	Nico Huber
2018-10-22	reset: Convert individual boards to `board_reset()`	Nico Huber
2018-10-19	soc/lowrisc: Remove the remains of a LowRISC soc	Peter Lemenkov
2018-10-19	soc/intel/cannonlake: Enable HDA driver support	praveen hodagatta pranesh
2018-10-18	mediatek/mt8183: Add EMI init for DDR driver init	Huayang Duan
2018-10-18	mediatek/mt8183: Add register definitions of DRAM controller	Tristan Shieh
2018-10-18	cpu/amd: Use common AMD's MSR	Elyes HAOUAS
2018-10-18	soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIG	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double definition for wideio	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove DEV_D18F4 definition	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double defined GPIO MMIO bases	Richard Spiegel
2018-10-18	amd/stoneyridge/include/soc: Re-arrange NB IOAPIC definitions	Richard Spiegel
2018-10-18	soc/amd/stoneyridge/smi.c: Prefer using '"%s...", __func__'	Richard Spiegel
2018-10-18	soc/amd/stoneyridge/southbridge.c: Change comparison order	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove "else" after a return	Richard Spiegel
2018-10-18	intel/common/block: Fix issue found by klockwork	John Zhao
2018-10-18	soc/intel/skylake: Prevent disabling of TCO	Naresh G Solanki
2018-10-17	soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions	praveen hodagatta pranesh
2018-10-17	soc/intel/cannonlake: Add new cannon lake PCH-H support	praveen hodagatta pranesh
2018-10-17	mediatek/mt8183: Add USB support	Jumin Li
2018-10-17	mediatek: Refactor USB code among similar SoCs	Tristan Shieh
2018-10-17	soc/cavium/cn81xx: Drop dead do_soft_reset() implementation	Nico Huber
2018-10-14	soc/amd/stoneyridge: Define PM USB Enable register	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Remove hudson EHCI debug controllers	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Rearrange southbridge.h more	Marshall Dawson
2018-10-12	drivers/intel/fsp2_0: Hook up IntelFSP repo	Patrick Georgi
2018-10-12	amd/stoneyridge: Fix PmControl register size in SMI handler	Marshall Dawson
2018-10-12	amd/stoneyridge: Rename CGPLL_CONFIG definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Rename GppClkCntrl fields	Marshall Dawson
2018-10-12	amd/stoneyridge: Rearrange southbridge.h	Marshall Dawson
2018-10-12	amd/stoneyridge: Remove dead GPIO definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Clarify XHCI_PM register definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Fix SPI_CMD_TRIGGER coding style	Marshall Dawson