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2015-04-02urara: Fix CBFS header definitionsVadim Bendebury
Urara CBFS header configuration is broken. CBFS header needs to be right above the bootblock, and the CBFS data - 0x100 bytes above, to allow room for proper CBFS wrapper structures. Ideally only the header offset should be specified (and even that could be derived from the bootblock size). But this is a more generic problem to be addressed with different architectures' image layout requirements in mind. BRANCH=none BUG=chrome-os-partner:31438 TEST=coreboot image passes the integrity check now (it was failing before because CBGS header was overlaying the bootblock) $ FEATURES=noclean emerge-urara coreboot $ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \ /build/urara/firmware/coreboot.rom.serial $ cbfstool /build/urara/firmware/coreboot.rom.serial print coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100 alignment: 64 bytes, architecture: mips Name Offset Type Size fallback/romstage 0x4100 stage 7100 fallback/ramstage 0x5d00 stage 18995 config 0xa780 raw 2452 (empty) 0xb140 null 1003096 Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67 Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227523 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhzjinkun.hong
Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02rockchip: support pwm regulatorhuang lin
BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9240 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02rockchip: support i2c clock settinghuang lin
BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02veyron_pinky: Add rev2 support, clean up mainboard.cJulius Werner
This patch adds support for the board changes in rev2 (board_id = 0001). It also moves the existing mainboard.c code around a bit to group it by component. BUG=chrome-os-partner:32139 TEST=Booted on rev1. Confirmed SD card still works. Confirmed power button was still as broken as before. Original-Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220251 (cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8d3479aa314f8c6f1591c1b69b0a3827234fc730 Reviewed-on: http://review.coreboot.org/9237 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02veyron: select rw romstage using vboot2Daisuke Nojiri
this change makes veyron pinky to select a rw romstage using vboot2. BUG=None TEST=Booted Veyron Pinky. Verified firmware selection in the log. BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> CQ-DEPEND=CL:219100 Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f Original-Reviewed-on: https://chromium-review.googlesource.com/219103 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475 Reviewed-on: http://review.coreboot.org/9234 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Disable ADSP power gating feature by defaultDuncan Laurie
Disable ADSP D3 and SRAM power gating features by default, and make the devicetree.cb flags into enable flags instead of disable. BUG=chrome-os-partner:31588 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Ibda298b995b07a2826a406e74e0d244b1fd97746 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b81ef37c036d61dc56e650796227dcc84a7ccc89 Original-Change-Id: Ib881290acc07819b55d776d4696bf0062df4d50e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9218 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Add event log entry for GPIO27Duncan Laurie
Add event log entry if GPIO27 is used to wake the system. This GPIO is treated separately from other GPE and it is one of the only events that can wake from Deep Sx. BUG=chrome-os-partner:31549 BRANCH=samus TEST=samus: suspend/resume and wake from keypress, check for GPIO27 event in event log. Change-Id: If699640701b0afcd0843c2a99546ee6bb9d09361 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0f1cccfd00552dafbaa91acc362b5e35474c3a95 Original-Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220323 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Reg_Script: add END tag to array "smbus_init_script"Ryan Lin
Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script. BUG=chromium:416651 TEST=test on Auron. Change-Id: Ieeaf6c705aa673acc9bb2635e103c4148bc8742f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 172c5fc259a2f6d09daccb1fe53fe0aa7c5601e1 Original-Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220934 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Synchronize for power management with FRCKenji Chen
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration. BUG=chrome-os-partner:31424 TEST=Build an image, and check the procedure and recommended setting is applied correctly. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4 Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2 Original-Reviewed-on: https://chromium-review.googlesource.com/219994 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRCKenji Chen
OBFF: Disable it by clearing bit fields in that W/O register. RO: Enable Relaxed Ordering from each enabled Root Port. Linker Arbiter: Set it to recommended setting. BUG=None TEST=Build an image and check the setting are applied correctly on Samus. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c Original-Reviewed-on: https://chromium-review.googlesource.com/219993 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9210 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Broadwell: Revise programming flow for write-once registersKenji Chen
Extended PCIe Capability and Advanced Error Report locates at offset 0x100 is W/O, and the subsequent write following the 1st write to the register takes no effect. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9 Original-BUG=chrome-os-partner:31424. Original-TEST=Build a image and check the programming value is correct on Original-Samus. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db Original-Reviewed-on: https://chromium-review.googlesource.com/219985 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844 Reviewed-on: http://review.coreboot.org/9209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Configure IOSF Port and Grant CountKenji Chen
Synchronize the code with FRC. Change-Id: I50d2a02971681bbfcf4135482b5b95a41ddaac36 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c891a3e0474235bd97268f52d09ddff574caeb95 Original-BUG=None Original-TEST=Build coreboot image and run on Samus to confirm the setting is properly applied. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3 Original-Reviewed-on: https://chromium-review.googlesource.com/219523 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Samus: Synchronization with FRC to enable PCIe Relaxed Order.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324 Original-BUG=None Original-TEST=Modify settings, build and update the image to Samus and Original-check the settings are applied to Registers. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Original-Reviewed-on: https://chromium-review.googlesource.com/219073 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31 Reviewed-on: http://review.coreboot.org/9206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan
Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands for these processors. Pre-conversion materials are compatible with USB PLL VCO current increase. Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL VCO current. BUG=chrome-os-partner:31199 TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register has new value. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0 Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211337 Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d) Original-Reviewed-on: https://chromium-review.googlesource.com/205970 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217772 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6 Reviewed-on: http://review.coreboot.org/9200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Update PCIe configuration to follow BWGKane Chen
According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Clear pending GPE events before entering sleep stateDuncan Laurie
In the case of an EC wake event that is pending but not cleared it is possible for the EC wake pin (i.e. GPIO27) to be asserted after the kernel triggers the sleep SMI but before the system goes to sleep. If this happens then the GPE will be reported as a wake source when the system wakes up again. BUG=chrome-os-partner:33218 BRANCH=samus,auron TEST=build and boot on samus, use the keyboard to enter suspend with suspend_stress_test and ensure that only the RTC is listed as a wake source upon resume. Change-Id: Id900132bb81e4cf50885a652ed00a142d951ea4d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 50396ab6a3a3efb3b3dea4f1c2a8f8804fed943e Original-Change-Id: I319dc22e21126a3086415f8f8b2b35eaec66fd50 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225540 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Baytrail: Change PCIe root disable algorithmKenji Chen
Disable Root Port0 only when there is no PCIe device present on any root port. BUG=None TEST=Boot Rambi with PCIe installed/non-installed on RP0 to confirm the RP0 is correctly enabled/disabled. However, I still need someone to help check if RP0(no device) is still enabled if there is device on other RPs since since I have no devices having slots from RP1/2/3. Change-Id: Iae552975250ed6f309c423b847621b8994172891 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217791 Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Baytrail: add _PRT to each PCIe root port deviceTed Kuo
Report PCI routing table of all PCIe root ports for legacy interrupt. Some PCIe devices using legacy interrupt can't work if PCI routing table isn't defined. It's necessary and defined in BWG Chapter 28.1.3. BUG=chrome-os-partner:31943 TEST=compiled and tested BRANCH=NONE Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I2c684edfd1fc624bed471783584250cd9f5e66f5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9040d564a32607327057a84b9aab14e66cd5b45 Original-Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b Original-Reviewed-on: https://chromium-review.googlesource.com/218422 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Ted Kuo <tedkuo@ami.com.tw> Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Reviewed-on: http://review.coreboot.org/9201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02ipq806x: provide soc specific CBMEM_CONSOLE_PRERAM_BASEVadim Bendebury
For now storm bootblock runs with DRAM fully initialized, this patch puts the early console between bootblock and rom phase. BUG=chrome-os-partner:31734 TEST=verified that preram_cbmem_console is set: $ grep preram_cbmem_console cbfs/fallback/bootblock.map 40618000 A preram_cbmem_console Change-Id: I2d63f5fde0d3794062068289c648d8bcda11a9a3 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6bdadad3787d6a4a2d4828b0f300455fedca2b8d Original-Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217291 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Add reporting of broadwell MCH revisionDuncan Laurie
Since the E0 and F0 stepping parts have the same CPUID it is necessary to use the MCH PCI device revision to determine what the actual stepping is. Add this decode table so the early output gives proper identification of the installed CPU type. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus with E0 and F0 parts Change-Id: Idce1e289cd958c77febc87395f27570247512a87 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a5346141e45b105a35a7641f60b29e02ab2bdfa3 Original-Change-Id: I1bc127badd75ecc34d3d2dbae5d272bd4d9f9082 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223158 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9228 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Change CPUID 306D4 to report "E0 or F0"Duncan Laurie
The F0 stepping has the same CPUID as E0 stepping so report it as either stepping to avoid confusion. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I99a83855b4393d736724836b709702417483b5d2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 55ed3bc880c31c0ca5c8a21c335722af05eb57f7 Original-Change-Id: Ia4955f346ceb9be92e06ecea5b7a8fe2db84cabc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: me: Fix typo and add missing phase stateDuncan Laurie
Fix the typo of sate to state and add uKernel phase to just output the current state byte. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5f341ee6c58487aeb927cab0641742cb4071a6b7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de6149508c50d0770fedfbe352e9149abea87b4c Original-Change-Id: I520a4cc75faffa5feeb6113ffd7b07a48c4e6f28 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222677 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
Some of the files which include cbfs_core.h don't even need the header definition while others just need the cbfs API which can be obtained from cbfs.h. Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9126 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-30broadwell: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
When building HAVE_REFCODE_BLOB there are a couple of errors. One is a failure building !CHROME_OS. The other is from a header change where console_tx_byte() was declared. Change-Id: I4110debd6d3818d4a803ed22037166c226f2ed11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9142 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-30baytrail: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
When building HAVE_REFCODE_BLOB there are a couple of errors. One is a failure building !CHROME_OS. The other is from a header change where console_tx_byte() was declared. Change-Id: Ia912902e8276d13b8e1716aa16c57b111579a03d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9141 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30imgtec/pistachio: Bring uart driver to modern standardsPatrick Georgi
The console interface changed in upstream, and the driver didn't reflect that yet. This wasn't obvious because the driver wasn't compiled at all. Change-Id: Id18391e62e7ebd8f5fc929838ce27bf414e364f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9165 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28pistachio: don't open code ramstage loadingAaron Durbin
Use the run_ramstage() function to load and run ramstage. Change-Id: I783801bf506fa2f9608eefe1cd20257292c80af5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28storm: need larger CBFS cacheVadim Bendebury
With VPD blob of certain format, CBFS cache on storm proves to be not large enough. This patch makes it bigger, it is still well above the area preserved for the NSS. BUG=chrome-os-partner:32152 TEST=the system now boots with the VPD it used to fail booting. Change-Id: Iee1214b218ee3f8aca28797841501c227549affb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f19ca8cb9a2efa1d295f038730ed06ec9ceb8c4 Original-Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219572 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Add support for pmc_rst_status get and printFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully and pmc rst status POR is seen. Change-Id: Ic09cb46d9be7670e467543e42b251efb1a4313d0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5dbfae6bbc0f4f30e216e37b515f4120f7833a38 Original-Change-Id: Id0c2b208222deaf099b8938ba583551979588d52 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220721 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Replace use of clk_rst with CLK_RST_REGFurquan Shaikh
Also, get rid of unused clk_rst variables. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I6487162454159a81b31fe0d6d39c2bdbed3f859a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030081fe85fc9609fdf2003cf51b7350e08f0429 Original-Change-Id: I880ae5c396c33006f6b184cca7f171e4373f4016 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220720 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: measure romstage timingsAaron Durbin
Measure the MTS load time, MTS initialization time, and the ramstage verification/load time. BUG=None BRANCH=None TEST=Booted and noted timings. Change-Id: I1eb1e3a73316a3fa76ef8e73314bedde34c6c582 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b5b34a3abd388359b7d1cba5a858e4e5a402b476 Original-Change-Id: I71119689182e86406d5052f007908152d41e9092 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219715 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9103 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132/rush/ryu: Use CLK_RST_REG instead of &clk_rst->...Furquan Shaikh
BUG=chrome-os-partner:31821 BRANCH=None TEST=Built and booted to kernel prompt on ryu. Rush compiled successfully. Change-Id: I63ba55c53094c185d72dcb5c5d0d766461989806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a9aa565244bae5659e458ea90064eb5b803d574 Original-Change-Id: I5b00fbcb8e414c67563f1ad548f84c281898f939 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219392 Original-Reviewed-by: Tom Warren <twarren3959@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Clean up clock register writesFurquan Shaikh
Clean up functions to write to clk_enb and rst_dev registers and add clock_disable and clock_set_reset functions to provide a complete API for updating the registers. BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles successfully on rush Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183 Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219191 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9099 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28Ryu: Move I2C6 init to ramstageTom Warren
BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639 Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28Ryu: Rewrite I2C6 mux initTom Warren
Do the absolute minimum needed to allow the DPAUX mux ctl write for I2C6. This leaves HOST1X off (reset and clock disabled) to avoid a conflict with any kernel display driver init. I2C6 init/enable will be moved to ramstage in the next CL. BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I42106778a26c5a1d1483cc308b8314599c391539 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9093 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove private spin table implementationAaron Durbin
Support the generic spin table code instead of having the one-off implementation. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel w/ smp. Both w/ and w/o secure monitor. Change-Id: I8557298d1a159b70818cbd8864470ff0d8a46fb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d89af95a7919f0b8acc92d82f3abda965514ccf Original-Change-Id: I24d56a30fdabd7a35ebc28dcc355c675de823a51 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218655 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9085 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: Add secmon supportFurquan Shaikh
BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and secmon loads and jumps to payload successfully. Change-Id: I929cf2c938fb5d8c20e13fbd1fdbd349378914ff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2e5d6adc63c4d820417985e34f1f04810b38422b Original-Change-Id: I442546178ad945e7639a99dd2943d13a69b06d09 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214372 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9081 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: use generic GIC driverAaron Durbin
As the arm64 boot flow handles initializing the GIC by way of the driver provide the SoC support for that driver and use it. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel on ryu. Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217514 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28arm64: Replace CONFIG_* variables with {read/write}_currentFurquan Shaikh
Instead of relying on config variables to determine the current el, use {read/write}_current macros for accessing registers. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and boots to kernel login prompt Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564 Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217148 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: update MTS version formattingAaron Durbin
Nvidia tracks their MTS versions using decimals. Update the format so there isn't an extra step in communicating versions while debugging things. BUG=chrome-os-partner:31864 BRANCH=None TEST=Booted and confirmed decimal print out. Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35 Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217260 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove bring_up_secondary_cpu chip optionAaron Durbin
Now that there is cpu devicetree support retire the bring_up_secondary_cpu option as the devicetree is the way going forward to do other CPU bring up. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted with 2nd core. Change-Id: I3e8812cd2183f2126c11c36ff4844c15b3cbfc1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7eab33b763d33d6be210ddb69e3c67411bad0fd0 Original-Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216929 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: add support for smbios type17 in broadwellKane Chen
This change also depends on mrc due to changes in pei_data.h Report smbios type 17 for each memory CQ-DEPEND=CL:210005 BUG=None BRANCH=None TEST=Compiles successfully See smbios type17 in OS by dmidecode Original-Change-Id: If83c99364726cd17c719a59ed8ac993736c63b9a Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210399 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 6da6b4ffb3a45fdd766b88220c2adb168b3c5e10) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I39ea9ef9b342239fe26846ab0a928f6a680c21e8 Reviewed-on: http://review.coreboot.org/8956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-27rk3288: Add GPIO() macroJulius Werner
The static gpio_t initializers are stylish, but they are still a little too annoying to write and read in day-to-day use. Let's wrap that in a macro to make it a little easier to handle. BUG=None TEST=None Change-Id: If41b2b3fd3c3f94797d314ba5f3ffcb2a250a005 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 102a5c0a800f43d688d11d1d7bbc51e360341517 Original-Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220250 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27rk3288: Add missing #include and use uniform typesDavid Hendricks
This updates timer.h to #include the header necessary for u32, and to change the one instance of uint32_t to u32 to be uniform. BUG=none BRANCH=none TEST=compiled Change-Id: I4d67045206fd94985774b8d46a307bbb2e337f30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ff2629fdf3c69c203fa61ec894bb4895990cb5e Original-Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220612 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27soc/imgtec/pistachio: Add IMGTEC SPI controller driverIonela Voinescu
The Serial Peripheral Flash Interface (SPFI) block allows communication with various devices over the SPI bus. It uses a configurable transaction interface and it clocks the bus according to the configured command, address, gap (aka dummy) and data lengths. This controller requires the SPI_ATOMIC_SEQUENCING flag set (write and read done in the same transaction) as it cannot directly control CS and will assert/de-assert CS at the beginning/end of a transaction itself. Note that the size of any transfer cannot be greater than 64KB - 1, as this is configured in a 16-bit field. The SOC has 2 SPFI interfaces each of them providing 5 slave select lines. SPFI 0 supports single and dual modes, SPFI 1 supports single, dual and quad modes. For SPFI interface 0: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi0clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set - CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim0_d0_txd MFIO_MIPS_10 0 spim0_d1_rxd MFIO_MIPS_9 0 spim0_mclk MFIO_MIPS_8 0 spim0_cs0 MFIO_MIPS_2 1 spim0_cs1 MFIO_MIPS_1 1 spim0_cs2 MFIO_MIPS_55 1 MFIO_MIPS_28 1 spim0_cs3 MFIO_MIPS_56 1 MFIO_MIPS_29 1 spim0_cs4 MFIO_MIPS_57 1 MFIO_MIMPS_30 1 For SPFI interface 1: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi1clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set - CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim1_d0_txd MFIO_MIPS_5 0 spim1_d1_rxd MFIO_MIPS_4 0 spim1_mclk MFIO_MIPS_3 0 spim1_d2 MFIO_MIPS_6 0 spim1_d3 MFIO_MIPS_7 0 spim1_cs0 MFIO_MIPS_0 0 spim1_cs1 MFIO_MIPS_1 0 MFIO_MIPS_58 1 spim1_cs2 MFIO_MIPS_2 0 MFIO_MIPS_55 2 MFIO_MIPS_31 1 spim1_cs3 MFIO_MIPS_56 2 spim1_cs4 MFIO_MIPS_57 2 BUG=chrome-os-partner:31438, chrome-os-partner:32441 TEST=Tested as bare-metal driver on Pistachio FPGA Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91 Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217320 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9049 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: use proper SOC nameVadim Bendebury
Danube has become Pistachio, let's rename all instances where this SOC is mentioned. BUG=none TEST=board urara still builds Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78 Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220401 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support arm64 SMP bringupAaron Durbin
Use the formal devicetree way for bringing up each of the cpus. This includes providing a cpu_driver as well as calling arch_initialize_cpus() with the proper operations to start the cores. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP on ryu. Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216926 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 12:45:03 +0000