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path: root/src/southbridge/amd/agesa/hudson/smi.c
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2018-05-29src/southbridge: Add and update license headersMartin Roth
This change adds and updates headers in all of the southbridge files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all southbridge directories. Change-Id: I09614730bfd4db923dda103bd07bab02836a4c92 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2014-04-18southbridge/hudson: Compile refactored SMI setup utilities in SMMAlexandru Gagniuc
Refactor hudson_enable_gevent_smi() to allow configuring the interrupt mode and trigger level. Move the utilities which are useful in SMM to a separate file that is included in both ramstage and SMM. This is useful for SMI handlers which need to enable or disable GEVENT SMIs on-the-fly. A follow-up patch makes use of this infrastructure. Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/170 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17southbridge/hudson: Add support for ACPI enable/disable via SMIAlexandru Gagniuc
This enables the ACPI SMI command port in the FADT table, and sets up the hardware accordingly. If we have SMI enabled, then we don't set the SCI_EN bit at boot, causing the OS to send the ACPI_ENABLE command, as required by the ACPI spec. This gives us a chance to hook into the mainboard_smi_apmc() handler. Change-Id: Ib4c63d55b3132578dcae48bfe2092d4ea35821dd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5511 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17southbridge/amd/agesa/hudson: Add initial support for SMMAlexandru Gagniuc
This sets up the infrastructure to handle SMIs generated by the Hudson southbridge. An API for interfacing to mainboard handlers is not defined at this point. A few functions are defined to allow mainboard code to enable SMIs from GEVENT pins. These are the only functions which I expect to be needed anytime in the foreseeable future. SMIs are always acknowledged and cleared, as not clearing an SMI will cause us to re-enter the SMI, effectively bricking the machine if a southbridge-generated SMI without a handler occurs. Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5494 Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: build bot (Jenkins)