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Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11083
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Bring http://review.coreboot.org/#/c/10582/ to Hudson
Change-Id: I1ba3047699c304a769215fe901dc3511bf23199d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11022
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and
(presumably) not used very often, add support for hiding it:
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03) USB1 (3.0, XHCI)
00:10.1 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03)
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB2 (2.0, OHCI+EHCI)
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB3 (2.0, OHCI+EHCI)
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB4 (1.1, OHCI only)
Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/7355
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The location of the AMD ROMSIG binary was being checked and warnings
were being printed even when the ROMSIG file wasn't being used.
These false warnings are avoided by moving the warnings into the
block where the CBFS file for the ROMSIG is generated.
Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11161
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead
check to make sure they're defined and not zero. In some cases, zero
might be a valid value, but it didn't look like zero was valid in these
cases.
Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS.
This can be extended to other Kconfig values for CBFS.
Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10683
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch calculates the address where the chipset firmware descriptor
should be located and compares it against the actual value from Kconfig.
If the two don't match, it puts up a warning.
This could probably replace the config variable completely, but I wanted
to see how other people felt before doing that. I seem to recall that
the value used to be calculated, so I figure that there must be a reason
it's done this way at this point.
If we do want to keep the Kconfig setting, this patch could also be
modified to just verify that the HUDSON_FWM_POSITION is inside the ROM
space.
Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Resync together, backporting a fix for the initialization of
8254 and 8259, as in commit 8d9a1bd5. Also fix a typo and
reduce out useless whitespace differences.
Change-Id: I9a9b1fb9083c5417a8d061f90a89074f2a601ddf
Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reported-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10453
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.
For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.
Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10317
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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All boards now use per-device ACPI. This patch finishes migration
by removing transitional kludges.
Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7372
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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There's now room for other repositories under 3rdparty.
Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.
In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.
This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).
Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In agesa code for hudson southbridge LPC_DEV is not defined,
but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800.
This fixes it.
Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: http://review.coreboot.org/9292
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
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Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.
Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.
In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.
Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7961
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).
Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
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This replaces acpi_is_wakeup_early().
Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8187
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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This patch has a rather twisted history. It was originally split off
from a chromium patch, which moved ALTCENTURY to Kconfig. However,
since we have no user without ALTCENTURY, we've agreed that the best
way to proceed is to eliminate the non-ALTCENTURY case entirely.
The old commit message and identifiers are kept below for reference:
The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.
BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the second half the following patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7987
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7839
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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It appears the decimal value was used instead of the hex value.
Change-Id: I04acde9e5b2a9e08ed01b0564c3d561b0385a392
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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They were only used internal to the SPI drivers and, according to the comment
next to their prototypes, were for when the SPI controller doesn't control the
chip select line directly and needs some help.
BUG=None
TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan.
BRANCH=None
Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192048
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627
Reviewed-on: http://review.coreboot.org/7708
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Don't build in non-essential blobs by default. However, if the user
selected to use the blobs repository, then default to including the
blobs.
Change-Id: Ie90f00d7c18d725f24fe1503fadaf098d3cefa4a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7638
Tested-by: build bot (Jenkins)
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Change-Id: I009a01d3324d48d2eeda87d74c8e3e7c27958ee2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5525
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Change-Id: I390c14b3e145dab45b96e25833fe5fed2e5a0adc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7637
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Split FCH parts to southbridge/hudson.
Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7159
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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GPP config from devicetree.cb is not implemented for fam15tn/fam16kb.
Also only for asus/f2a85-m the configuration value matched the actual
programming.
Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7600
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ic6affae7e508f28b131c7d07191289f4fcbf2d74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7599
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I2adb5a8fe2cede988cc6fdef5ff81da86d267175
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7624
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I39edaaed67f45e7c56ec02c2aac2a4c5e1b63bc7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7586
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Change-Id: Icc2e7b66b3ff5f70b219a3e67494ce3df055c9d5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7033
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Avalon support now lives under pi/avalon so we can restore Hudson
to the state before it was added there.
Change-Id: Id96973f3458fae162232c160e602595b58c43027
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7389
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.
Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.
Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
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Expose one CONFIG_ variable instead of seven to C preprocessor.
Change-Id: Ib815127561d320a5e8f8e6ef168933d81809521e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7494
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ide31d53b3334bae3f19c75ad0c4584d601838f8f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7379
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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There are too many differences, and calculating relatively
large integer using floats might not be the brightest idea
anyway.
Also avoid relying on ls(1) output format to determine file sizes.
Change-Id: I5f96c036737b74e20f525c3dc9edc011ad403662
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7447
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7193
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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IMC fan control should be enabled after OS launched.
I have tested on OliveHill and Parmer with Windows 7 and Ubuntu 13.10.
Change-Id: I16d6ff6b1272d16b840e803e0a95f6e363c79704
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/7165
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The fan can stop but can't run again. "AGESA: Call get_bus_conf() just
once" (commit ef40ca57) results to this problem.
This patch can resolve this problem.
Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6981
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.
This CL also opportunistically cleans up some style problems in this file.
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)
Removed the addition of stdint.h to mc146818rtc.h since
types.h is now included. Changed rtc_init to cmos_init for
fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.
Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Remove northbridge specific callouts for AGESA_READ_SPD.
Move low-level SMBus code to southbridge.
Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7112
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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As currently many systems would be barely functional without ACPI,
always generate ACPI tables if supported.
Change-Id: I372dbd03101030c904dab153552a1291f3b63518
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4609
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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00730F01 contains the Avalon southbridge and a Platform Security
Processor (PSP). Supporting the PSP requires specific binaries to
be included in the ROM. The fletcher utility is used to sign PSP
binaries.
The IMC access routines are not accessible for newer AMD parts that
use pre-compiled AGESA. Change the Hudson code such that the IMC
code is not compiled if IMC is not selected in Kconfig.
Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled.
The newer AMD mainboards will initially be released without ACPI
resume support (S3) due to the use of AGESA internals in the
existing Hudson routines. The Makefile change allows newer
mainboards to avoid the API issues.
Change Kconfig such that the FWM flag is always set for PSP-enabled
parts. This has the side effect of forcing the generation of the
FWM directory in the absence of GEC, IMC, and xHCI.
Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6677
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
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Found by Cppcheck 1.65. Fixes:
(warning) Variable 'processor_name_string' is reassigned a value before the old one has been used. 'break;' missing?
(warning) Variable 'rsize' is reassigned a value before the old one has been used. 'break;' missing?
Change-Id: I4a5c947fd5cc5797eb026475ec7036bc5eaf58db
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper
while AMD_INIT_ENV was already handled as part of BiosCallouts.
OEM configuration is supposed to be implemented as part of BiosCallouts,
leaving agesawrapper agnostic of platform details.
TODO: S3 resume for XHCI1.
Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6241
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
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