coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-07-19	src: Make implicit fall throughs explicit	Jacob Garber
2019-07-16	sb/amd/{cimx,}/sb{700,800,900}: Prevent uninitialized reads	Jacob Garber
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-11-16	src: Remove unneeded include <cbmem.h>	Elyes HAOUAS
2018-05-20	sb/amd/cimx/sb800: Get rid of device_t	Elyes HAOUAS
2018-04-29	sb/amd/cimx/sb800: Remove unused variable	Paul Menzel
2018-04-29	sb/amd/cimx/sb800/lpc: Shorten and wrap long lines	Paul Menzel
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-12-17	southbridge/amd agesa & cimx spelling fixes	Martin Roth
2014-06-11	amd/southbridge/lpc: SPI BAR has fixed size/location	Dave Frodin
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-12-12	Fix SPI BAR special case in lpc_set_resources	Martin Roth
2012-11-28	Remove assembly coded log2 function	Ronald G. Minnich
2012-04-12	Add Southbridge support for S3.	zbao
2012-04-12	Unify IO APIC address specification	Patrick Georgi
2011-09-07	AMD F14 southbridge update	Kerry She
2011-06-22	Rename {CPU\|NB\|SB}/amd/*_wrapper folders	efdesign98