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Some coreboot project code with my work
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Age
Commit message (
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Author
2015-02-15
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
Kevin Paul Herbert
2015-02-14
southbridge/amd/pi: Combine and correct the IRQ text strings
Dave Frodin
2015-02-05
southbridge/amd/pi: write_hpet requires additional config option
Dave Frodin
2015-02-05
southbridge/amd/pi: Update Kconfig and makefiles for bolton
Dave Frodin
2015-02-05
southbridge/amd/pi: Add the bolton definitions
Dave Frodin
2015-01-27
southbridge/amd/pi: Clean up whitespace in Kconfig
Dave Frodin
2015-01-27
southbridge/amd/pi: Rename Avalon to Hudson
Dave Frodin
2015-01-27
southbridge/amd/pi: Correct several path names
Dave Frodin
2015-01-27
southbridge/amd/pi: Correct several yangtze/avalon typos
Dave Frodin
2015-01-10
AMD binaryPI: Drop ramtop via nvram
Kyösti Mälkki
2015-01-09
AMD binaryPI 00730F01: Switch to per-device ACPI
Kyösti Mälkki
2014-12-30
drivers/pc80/mc146818rtc: Assume we always have ALTCENTURY
Gabe Black
2014-12-19
AMD 00730F01: Change Makefile to use BLOB sizes for packing
Bruce Griffith
2014-12-16
southbridge/amd/pi/avalon/pci_devs.h: Correct define `EHCI3_DEV`
Paul Menzel
2014-11-20
AMD: Isolate AGESA and PI build environments for southbridge
Kyösti Mälkki