coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-08-05	AMD SB: Call the rtc update if needed (Propagation)	zbao
2012-05-08	Clean up #ifs	Patrick Georgi
2012-04-12	Unify IO APIC address specification	Patrick Georgi
2012-02-20	Force SB800 bootblock to use I/O for PCI config	Dave Frodin
2012-02-17	amd/sb800: Move HAVE_HARD_RESET to southbridge	Patrick Georgi
2011-10-31	Fix usb debug dongle support	Sven Schnelle
2011-10-28	Get rid of the old romstage-as-bootblock ROM layout	Patrick Georgi
2011-07-14	Set SB800 ROM decode size based on kconfig.	Marc Jones
2011-04-18	* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value	Stefan Reinauer
2011-02-12	Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early on...	Rudolf Marek
2011-01-28	Fix Bimini build	Stefan Reinauer
2011-01-27	Trivial. Re-indent the code.	Zheng Bao
2011-01-27	Set the phy via weak function.	Zheng Bao
2011-01-25	Set the SB800 SATA PHY correctly.	Zheng Bao
2011-01-24	Change fadt revision back to 3.	Zheng Bao
2011-01-21	Now bimini can boot linux to login.	Zheng Bao
2011-01-20	S3 feanture of SB800. Compiliant with SB700.	Zheng Bao
2011-01-20	Move some board specific functions to sb800.h.	Zheng Bao
2011-01-20	This sb800 code is derived from sb700.	Zheng Bao