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broadwell_refcode
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Some coreboot project code with my work
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southbridge
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amd
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sr5650
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sr5650.c
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Author
2016-09-15
southbridge/amd/sr5650/sr5650.c: Update acpi_fill_ivrs
Martin Roth
2016-09-15
amd/sr5650: Update add_ivrs_device_entries
Martin Roth
2016-09-07
include/arch/acpi.h: change IVRS efr field to iommu_feature_info
Martin Roth
2016-08-31
src/southbridge: Code formating
Elyes HAOUAS
2016-07-31
src/southbridge: Capitalize CPU, RAM and ROM
Elyes HAOUAS
2016-01-04
sb/amd/sr5650: Correctly locate CPU MMCONFIG resource
Timothy Pearson
2015-12-18
southbridge/amd/sr5650: Add MCFG ACPI table support
Timothy Pearson
2015-11-23
southbridge/amd/sr5650: Add IOMMU support
Timothy Pearson
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-24
southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16
Timothy Pearson
2015-10-24
southbridge/amd/sr5650: Add optional delay after link training
Timothy Pearson
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2014-12-17
southbridge/amd amd81XX, cs553X & sr5650 spelling fixes
Martin Roth
2014-12-09
southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
Edward O'Callaghan
2013-04-11
AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment
Paul Menzel
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2011-11-01
remove trailing whitespace
Stefan Reinauer
2011-07-22
Update AMD SR5650 and SB700
efdesign98
2011-03-27
Add AMD SR56x0 support.
Zheng Bao