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broadwell_refcode
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Some coreboot project code with my work
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sr5650
Age
Commit message (
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Author
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-04-27
kbuild: automatically include southbridges
Stefan Reinauer
2015-02-15
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
Kevin Paul Herbert
2014-12-17
southbridge/amd amd81XX, cs553X & sr5650 spelling fixes
Martin Roth
2014-12-09
southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
Edward O'Callaghan
2014-07-29
Uniformly spell frequency unit symbol as Hz
Elyes HAOUAS
2013-04-11
AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment
Paul Menzel
2013-03-22
x86: Unify arch/io.h and arch/romcc_io.h
Stefan Reinauer
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-11-27
Get rid of drivers class
Patrick Georgi
2012-11-20
Unify use of bool config variables
Stefan Reinauer
2012-08-22
Auto-declare chip_operations
Kyösti Mälkki
2012-05-08
Some more #if cleanup
Patrick Georgi
2012-02-20
Fixes Fam10/SR5650 cpu not recognized message.
Dave Frodin
2011-11-01
remove trailing whitespace
Stefan Reinauer
2011-10-30
Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.
Stefan Reinauer
2011-07-22
Update AMD SR5650 and SB700
efdesign98
2011-03-27
Add AMD SR56x0 support.
Zheng Bao