summaryrefslogtreecommitdiff
path: root/src/southbridge/amd
AgeCommit message (Collapse)Author
2013-02-25AMD Southbridge: Add RTC init to lpc_initMike Loptien
Adding RTC init code to the Southbridge initialization code in 'lpc_init'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same edit made to the CIMX SB800 titled 'AMD/Persimmon: Add RTC init to CIMX SB800' with commit ID: c4d3d which can be viewed here: http://review.coreboot.org/#/c/2488/ Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2510 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-23AMD/Persimmon: Add RTC init to CIMX SB800Mike Loptien
Adding RTC init code to the Southbridge initialization code in 'late.c'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This was tested on a Persimmon but will apply to other mainboards as well. Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2488 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-21AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'Zheng Bao
Currently the size of the volatile storage for S3 reserved in the image is hardcoded to 32768 bytes. Make that configurable by introducing the Kconfig 'S3_DATA_SIZE'. As the storage space is needed for storing non-volatile, volatile and MTRR data, add a check if the size is big enough. Change-Id: I9152797cf0045c8da48109a9d760e417717686db Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2383 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-20Whitespace: Replace tab character in license text with two spacesPaul Menzel
For whatever reason tabs got inserted in the license header text. Remove one occurrence of that with the following command [1]. $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,' [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2460 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-19build system: Retire REQUIRES_BLOBPatrick Georgi
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory, builds failed when all files were configured to point to other sources. This change modifies the blob mechanism so that cbfs-files can be tagged as "required" with some specification what is missing. If the configured files can't be found (wrong path, missing file), the build system returns a list of descriptions, then aborts. Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19AMD S3: Change S3_VOLATILE_POS to S3_DATA_POSZheng Bao
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-18AMD S3: Fix typo vol*a*tile in southbridge KconfigZheng Bao
Change non-volitile to non-volatile. Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2437 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-11spi.h: Rename the spi.h to spi-generic.hZheng Bao
Since there are and will be other files in nb/sb folders, we change the general spi.h to a file name which is not easy to be duplicated. Change-Id: I6548a81206caa608369be044747bde31e2b08d1a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2309 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22Hudson: Legacy free question is hudson onlyMartin Roth
The "system is legacy free" question accidentally escaped from the hudson Kconfig where it was intended to stay and went coreboot-wide. This puts it back inside the boundries of the hudson southbridge where it belongs. I also commented the endif statements to make it easier to tell where things belong. Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2179 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-21Hudson: Cleanup - change SB800 references to hudsonMartin Roth
Go through southbridge/amd/agesa/hudson, thatcher and parmer mainboard directories and change all references to sb800 to reference hudson instead. This is just cleanup and should make no functional difference. Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2177 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-01-21Hudson: Changes to support agesa/hudson for legacy freeMartin Roth
Add Kconfig option for Legacy free and hook it into the parmer AGESA initialization as well as the FADT code. This should really be done inside the southbridge wrapper and not in the mainboard, but for now the code to attach it to is inside the mainboard. Update Kconfig for parmer and thatcher to default to legacy free. Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2157 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21Hudson: Changes to agesa/hudson FADT for ACPI 3.0Martin Roth
Update the southbridge/amd/agesa/hudson FADT generation for ACPI 3.0 compliance similar to what was done for cimx/SB800/fadt.c in commit 9aa4389. commit 9aa43892e6899b719fe7f4754901a0eae379a934 Author: Martin Roth <martin@se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT According to the datasheet, PMA_CNT_BLK is no longer available and PM2_CNT_BLK should not be used. Setup for these has been removed from the table and .h file. Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2140 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-09Fix typo in SB800 Kconfig for IMC positionMartin Roth
The cimx/sb800 IMC Firmware location Kconfig option has a typo which would could set it to the wrong location. Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/2120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-30rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_opsDenis 'GNUtoo' Carikli
That code will be used to disable the internal GFX card and enable the external PCIe card. The following lines from function `rs780_internal_gfx_enable()` are taken and reversed. /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c); l_dword &= ~(1<<0); l_dword |= 1<<1; pci_write_config32(nb_dev, 0x8c, l_dword); It has been tested on the M4A785T-M with the following card inside the PCIe 16x slot: 02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2) Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2065 Tested-by: build bot (Jenkins)
2012-12-29Add AMD Hudson blobs by CONFIG_REQUIRES_BLOBS dependencyMarc Jones
If a 3rd party blob option is selected, make sure that it makes the user select CONFIG_USE_BLOBS as otherwise the build will fail. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc Reviewed-on: http://review.coreboot.org/2080 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-28USBDEBUG: Enable the EHCI in AMD SouthbridgeZheng Bao
Since SB800, USB2.0 debug port is dev 0x12, func 2. Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1880 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-19No need to contact AMD for firmware anymorePatrick Georgi
We ship it in the 3rdparty repository. Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2060 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-12-14AMD S3: Rename generated s3.rom for make cleanZheng Bao
Add prefix coreboot_ to let make clean find it and delete it. Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2029 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-12SB800: Add IMC ROM and fan control.Martin Roth
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800 platforms. - Allows user to add the IMC rom to the build and to configure the location of the "signature" between the allowed positions. - Allows for no fan control, manual setup of SB800 Fan registers, or setup of the IMC fan configuration registers. - Register configuration is done through devicetree.cb. No files need to be added for new platform configuration. - Initial setup is for Persimmon, but may be extended to any cimx/sb800 platform. Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Rename generated hudson_romsig.bin for make cleanMartin Roth
The file generated when the IMC or XHCI binaries are included in the rom was named $(obj)/hudson_romsig.bin. The problem with this is that it doesn't get deleted when the user does a make clean. changing the name to coreboot_hudson_romsig.bin makes this happen. Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1978 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Fix SPI BAR special case in lpc_set_resourcesMartin Roth
There was already a special case for the SPI base address in lpc_set_resources for southbridge/amd/cimx/sb800 and southbridge/amd/agesa/hudson, but it needed to be modified to keep from killing the IMC rom during initialization. As soon as the BAR is disabled by setting the new base address, the IMC dies. The fix is to make sure it's still enabled when setting the new base address instead of setting the new address then re-enabling it. Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER to more accurately describe what we're using. Change-Id: I216d75b722c4332c239d487111a9880eabf59e91 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1975 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-12-12Claim the SPI bus before writes if the IMC ROM is presentMartin Roth
The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-01Drop TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I38ea2ed2be4d9240ec8cb6d5dc5b3cc578cdaefb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-30AMD S3: Leverage the public SPI routineZheng Bao
Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-27Enable the FCH GPP port prior to device enumerationDave Frodin
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1873 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20Unify use of bool config variablesStefan Reinauer
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-09Get rid of hard coded strings in ACPI tablesStefan Reinauer
(cosmetical) Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1748 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-07Fix whitespace issue with help message in Kconfig fileDave Frodin
Every line of text after a 'help' label in a Kconfig file must have the same whitespace preceding it, otherwise it's no longer considered help text. Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1687 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-10-08hpet: common ACPI generationPatrick Georgi
HPET's min ticks (minimum time between events to avoid losing interrupts) is chipset specific, so move it to Kconfig. Via also has a special base address, so move it as well. Apart from these (and the base address was already #defined), the table is very uniform. Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1562 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-07Remove chip.h files without config structureKyösti Mälkki
Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1473 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-28AMD Hudson: Printf the high address as unsigned integerZheng Bao
Some 32 bit machines print integer higher than 0x80000000 as negative number. Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1547 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-09-24AMD hudson: Round the float pointing number to integerZheng Bao
Try sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \ $1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \ od -Ax -t x On Linux with gawk, we get 000000 005500aa 000004 On FreeBSD with nongnu-awk, we get 000000 000055aa 000002 In awk, all the numbers are floating point number. So division doesn't round the result from 0.75 (3/4) to 0. And, There is a fact that, for the FreeBSD awk, sh> awk 'BEGIN {printf("%c", 0.75)}'; produces nothing, instead of 0. Here we need to convert the floating point number to integer by int(X), which is an awk built-in function, instead of GNU extension. Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-09-19cimx sb700: change Platform.h to remove some warningsSiyuan Wang
TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h, so we do some changes to remove such warnings. Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1499 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-17AMD Hudson: use awk to calulate instead of exprZheng Bao
Command expr in some systems only take 32bit as integer, which value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to calculate. And some system doesnt take hex value in Makefile, even in awk instruction. Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1527 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-08-30AMD S3: The offset of the nv storage depends on config.hZheng Bao
Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1485 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-28AMD hudson: Complete the missing ruleZheng Bao
Forgot to change the code back after debugging. Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1491 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-27SB700/SP5100: This configures the HPET clock period.Dave Frodin
Prior to this change the setting would be zeroes and would cause a BSOD in 64 bit versions of Windows. Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1475 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-27AMD Hudson: Move the combining firmware from Python to sh.Zheng Bao
Maybe sooner or later python is not a default tools to build coreboot. Most of the work is done by awk now. GNU extension of gawk is not used, isn't? echo, expr, printf, cat, awk, test, mv are the external tools. If XHCI, IMC or GEC firmware is not available and not defined, this script can skip integrating them. Change-Id: I9944b22b0b755672a46d472c355d138abafd6393 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1417 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-08Cleanup coreboot memory table includesKyösti Mälkki
The includes removed here were previously required for struct lb_memory and lb_add_memory_range(). Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1391 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-06AMD RS690: mark MMCONF resource as reserved MEMKyösti Mälkki
Use IORESOURCE_RESERVE to exclude the region from system RAM table. Change-Id: I61b51022165e1304a41554f67af75b3089d892af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1393 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-05AMD SB: Call the rtc update if needed (Propagation)zbao
Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1406 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-05AMD S3: Remove the hardcoded volatile positionzbao
Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1408 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-02AMD hudson: Call the rtc update if needed.zbao
Parmer and thather hang at windows 7 booting process. Setting the valid date in CMOS can fix that. Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1390 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-02AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_baseKyösti Mälkki
The code in rs690 or rs780 is always used with K8 or AMDFAM10 northbridge. Without GFXUMA, both of these set the same static value indirectly using the variable uma_memory_base. Make the register setting with immediate value, to remove the obscure use of variable uma_memory_base. Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1246 Reviewed-by: Zheng Bao <zheng.bao@amd.com> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-26Refactor driver structsPatrick Georgi
Our driver infrastructure became more flexible recently. Make use of it. These are the low hanging fruits (files with 5 device variants or more), but there are still lots of files with less potential for deduplication. Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1358 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-07-24cs5536: add smbus support in ramstageChristian Gmeiner
With this patch it is possible to use the smbus in ramstage. The biggest part of the patch is a simple code split into a general part (smbus.h) and the concrete users (early_smbus.c and cs5536.c). After the switch from romstage to ramstage the smb base address has changed, but that is no problem as the new base address is stored in bar0 of the ISA bridge. It could also be read via msr, but via PCI it is simpler. I used the following patch as reference on how to readout the new base address: http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1243 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-22Trinity wrapper code improvement.zbao
Set the default location of hudson firmware to 3rdparty. Move UMA code from mainboard to northbridge. Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1241 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-30 21:41:07 +0000