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2019-02-12sb/intel/common: Remove CAR_GLOBAL useArthur Heymans
We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: Ic2c90d264d851ab4abeca07f412d43d088ad96dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30506 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-01sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read()Kyösti Mälkki
Datasheets describe the used command as 'I2C Read' but adding the word 'eeprom' in between should avoid further confusion with other block commands. Followups will add a symmetrical pair of commands i2c_block_read() and i2c_block_write() that operate via I2C_EN bit and have a 32 byte size restriction on block transfers. For some hardware revision these block commands are available, while 'I2C Read' was not. Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-30sb/intel/common/firmware: Don't call GbE binary `firmware`Nico Huber
Unless things changed considerably, this file doesn't contain any firmware. It is merely replacing a configuration EEPROM for the MAC address etc. So don't call it firmware. Change-Id: Ife6190639e7f05da2cb6eddeb1b0db0e8ffc8e6e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-25sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that ↵Jan Tatje
need it Hide "Add gigabit ethernet firmware" option for boards that do not use GbE firmware in GbE section. The option is now hidden by default and can be reenabled on a per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the mainboards Kconfig. The following boards seem to use this: mb/roda/rv11 mb/ocp/wedge100s mb/ocp/monolake mb/lenovo/x230 mb/lenovo/x220 mb/lenovo/x201 mb/lenovo/x200 mb/lenovo/t530 mb/lenovo/t520 mb/lenovo/t430s mb/lenovo/t430 mb/lenovo/t420s mb/lenovo/t420 mb/lenovo/t400 mb/kontron/ktqm77 mb/intel/saddlebrook mb/intel/kblrvp mb/intel/dg43gt mb/intel/dcp847ske mb/intel/coffeelake_rvp mb/intel/camelbackmountain_fsp mb/hp/revolve_810_g1 mb/hp/folio_9470m mb/hp/compaq_8200_elite_sff mb/hp/8770w mb/hp/8470p mb/hp/8460p mb/hp/2760p mb/hp/2570p mb/google/sarien mb/facebook/watson mb/compulab/intense_pc mb/asus/maximus_iv_gene-z The boards were identified by looking at devicetree.cb, but this list is possibly still incomplete. Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-24sb/intel/common: More SMBus block_cmd_loop()Kyösti Mälkki
Setup to different block transactions are similar enough to have common place to call execute_command() in. Change-Id: I671fed280f47e6bc673eb7506f09ed6ed36d2804 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: SMBus block_cmd_loop()Kyösti Mälkki
For debugging prints, report the number of loop spent polling instead. Change-Id: I61865aaafc9f41acd85c5dc98817d12642965ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21121 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24sb/intel/common: SMBus complete_command()Kyösti Mälkki
Adds helper to test for SMBHSTSTAT flags for hardware having finished or failed a transaction. Change-Id: Idea15e03edde7aeedf198c1529f09c24a5bc0b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24sb/intel/common: SMBus execute_command()Kyösti Mälkki
Implement the common start of transaction. Fixes a problem where smbus_wait_until_active() can miss SMBHSTSTS_HOST_BUSY being set, if transaction completes very fast. Or if we are single-stepping or executing under SerialIce emulation. Change-Id: Icb27d7d6a1c54968950ca292dbae05415f97e461 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24sb/intel/common: SMBus setup_command()Kyösti Mälkki
Implements the common parts of any SMBus transaction with a stub to log and recover (TBD) from timeout errors. Bits in SMBHSTCTL register are no longer preserved between transactions. Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-22cpu/intel/model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-21drivers/spi: Add controller protection typeRizwan Qureshi
Some SPI controllers support both READ and WRITE protection add a variable to the protect API for the callers to specify the kind of protection they want (Read/Write/Both). Also, update the callers and protect API implementation. BUG=None BRANCH=None TEST=test that the mrc cache is protected as expected on soraka. Also tried if the read protection is applied correctly. Change-Id: I093884c4768b08a378f21242ac82e430ac013d15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-14mb/lenovo/[xtz]60: Introduce and use RCBA64 macroPeter Lemenkov
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14sb/intel: Use common RCBA MACROsPeter Lemenkov
This commit follows up on commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-10sb/intel/common: Show "Add EC firmware" only for boards that need itJan Tatje
Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to enable this option for boards that need it. The following list of boards requiring this was provided by Lijian Zhao: 1. intel/cannonlake_rvp 2. intel/coffeelake_rvp 3. intel/icelake_rvp 4. google/sarien 5. google/hatch Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-06Kconfig: Unify power-after-failure optionsNico Huber
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03sb/intel/bd82x6x: Move pcie ACPI code to a common placeArthur Heymans
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-29sb/intel/bd828x6x: Make CONFIG_ELOG=y compileArthur Heymans
The function pch_log_state() was overlooked when making the smi relocation code common. Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-19southbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-18southbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ic3f7d4d570cb5e343a9cf616e6e71935f9522b0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-05sb/intel: Fix pointer castsPatrick Rudolph
Fix some compiler warnings due to pointer to integer conversions with different size. Required for 64bit ramstage. Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05elog: make elog's SMM handler code follow everything elsePatrick Georgi
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in cpu/x86/smm.h Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03sb/intel/common: Create a common PCH finalise implementationTristan Corrick
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-28sb/intel/common: Fix style issue in spi.cElyes HAOUAS
Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27sb/intel/i82801gx: Use common Intel SMM codeArthur Heymans
Use the common Intel code to set up smm and the smihandler. This is expected to break S3 resume and other smihandler related functionality as this code is meant to be used with CONFIG_SMM_TSEG. Platforms (i945, pineview, x4x) using this southbridge will adapt the CONFIG_SMM_TSEG codepath in subsequent patches. Tested on Intel D945GCLF, still boots fine but breaks S3 resume support because it hangs on SMI. Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-26sb/intel/common: Fix style issue in spi.cPatrick Georgi
Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan T <stefan.tauner@gmx.at> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-26sb/intel/spi: read FLCOMP descriptor early and cache itStefan Tauner
Change-Id: I4e5fe3ff083f2d0db1cfde16550b57537d5f7262 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/c/28349 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-22sb/intel/common: Reset Pre-OP after atomic SPI cycle is finishedWerner Zeh
Make sure that the Pre-Op register is cleared when an atomic cycle has been finished without errors. Change-Id: Ied88337125b125474b411e2f39f668171d15bfac Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-07sb/intel: Deduplicate vbnv_cmos_failed and rtc_initPatrick Rudolph
* Move all implementations to into common folder. * Add rtc.c for rtc based functions Allows all Intel based platforms to use VBOOT_VBNV_CMOS. Change-Id: Ia494e6d418af6f907c648376674776c54d95ba71 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-07intel: Get rid of smm_get_pmbasePatrick Rudolph
Change-Id: I2b3168c600a81502f9cd1ff3203c492cf026e532 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-01sb/intel/common: Create a common implementation of `acpi_fill_madt()`Tristan Corrick
The function `acpi_fill_madt()` is identical among all the Lynx Point boards and sb/intel/bd82x6x, so share a common function between them. Earlier Intel platforms have similar implementations of this function. The common implementation might only need minor alterations to support them. Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No issues arose from this patch. Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-01sb/intel/common/pciehp.h: Add missing license headerElyes HAOUAS
Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29404 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logicJoel Kitching
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-20sb/intel/common/firmware: Ensure warning is put lateNico Huber
Change-Id: I400de0a622c2b45ea5ef1f1446f4f489ac397c32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28673 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-13src/*/intel: introduce warning when building with no IFDAngel Pons
Add a warning as suggested in patch CB:28233 with the "CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option. Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-23Kconfig, Makefile.inc: Remove all traces of ifdfakeAngel Pons
Since ifdfake has been deprecated in favor of better alternatives, there is no need to support it any further. Remove it from the build system. Change-Id: Id62e95ba72004a1e15453e3eb75f09cb8194feb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28233 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
This makes i82801ix use the common smm southbridge code to set up smm relocation and smi handler setup. This is needed in this change for the the smm relocation code relies on some southbridge functions provided in the common code. Some of the old code is kept for the Q35 qemu target. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Thinkpad X200: boots and going to and resuming from S3 still works fine. Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23419 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-28sb/intel/gpio: Cache gpiobase in ramstage and romstagePatrick Rudolph
Implement caching like it's done with pmbase. Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27664 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27sb/intel/common/pmutil: Use new PMBASE APIPatrick Rudolph
Change-Id: I0f37f0c49fd58adafd8a508e806e0f30759a6963 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27287 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27sb/intel/common/smi*: Use new PMBASE APIPatrick Rudolph
Use new PMBASE API functions in common SMI handler. Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-27sb/intel/common: Add functions to manipulate PMBASEPatrick Rudolph
Add common functions to manipulate PMBASE IO window. TODO: * Use the new functions to manipulate register in PMBASE. * Get rid of duplicated get_pmbase() Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27278 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25sb/intel/common/firmware: Enable me_cleaner for NehalemNicola Corna
Recent patches in coreboot have fixed the freeze issues related to the use of me_cleaner on Nehalem. However, at least on the Lenovo X201, with me_cleaner some PCIe devices (like the SATA and USB controllers) disappear. In particular, setting the AltMeDisable bit ("-S" or "-s" flag) makes them disappear completely, while unsetting it makes them disappear only during cold boots. This kind of behaviour was already observed by Youness Alaoui on the Purism Librem laptops ([1]), and it seems related to some required board-specific PCIe configuration in the ME's MFS partition. For this reason, on the Lenovo X201, "-w EFFS" has been added to the me_cleaner arguments, which whitelists the MFS-equivalent partition for ME generation 2. This fixes all the issues, and the PCIe devices work as expected. [1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/ Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/27178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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