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2018-05-14sb/intel/i82371eb: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-12-18i82371eb & qemu: Move to per-device ACPI.Vladimir Serbinenko
This one is special because qemu is really far from anything real but shares some common features. Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6939 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-29Tobias Diedrich wrote:Tobias Diedrich
> Stefan Reinauer wrote: > > The specified IO port is most likely wrong. As the comment mentions, the > > SSDT is a good place for that. A preprocessor define used both in the > > CPU init code and in the asl would solve the problem without an SSDT. > > For some info on CPU SSDT creation on intel check out > > src/cpu/intel/speedstep/acpi.c > > The IO port is ok (and I wrote the comment myself ;)): > DEFAULT_PMBASE is 0xe400 > PCNTRL reg offset is 0x10 > > Using the preprocessor will probably work too if iasl can do simple > arithmetic (likely yes), I'll look into that. BTW, my first idea was to use an acpi method that looks up pmbase in the pci cfg space, but when I define a method like this: Method(TEST, 2) { Return (Add(Arg0, Arg1)) } I get: |build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0, |0x01, TEST(0xe400, 0x10), 0x06) {} |Error 4096 - syntax error, unexpected PARSEOP_NAMESEG, |expecting ')' ^ While using the builtin Add() directly works. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-27After finding the missing bit poweroff works now.Tobias Diedrich
I cleaned up the patch and moved most of the dsdt.dsl and acpi_tables.c into the southbrige/northbridge directory. Updated patch should fix abuild error and incorporates suggestions on irc by uwe (thanks for the comments). Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch. Tested: Linux (poweroff, powerbutton event) XP (poweroff, powerbutton event) Abuild-tested Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09Remove various .c #includes from Intel 440BX/82371EB boards.Uwe Hermann
- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c into distinct compilation units, and don't #include the files anymore in romstage.c files. - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and northbridge/intel/i440bx/debug.c. - Add various header files which are now needed. - Make functions that need to be visible non-static. - Drop a remaining "select ROMCC" from a 4440BX board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-19Make ASUS P3B-F RAM init actually work by enabling SPD access.Uwe Hermann
On this board all reads from SPD return 0xff by default, there's a custom GPIO fiddling needed to enable access to the SPD SMBus offsets at 0x50-0x53. While coreboot actually sort of booted sometimes before r5193, that was just sheer luck as the RAM init was hardcoded in certain ways. Since the proper, more heavily SPD-based RAM init the brokenness of the ASUS P3B-F RAM init was becoming visible. This patch uses GPIOs to enable access to the SPD SMBus offsets, and resets the GPIOs again after RAM init (this is needed to allow for lm-sensors to work, for example). Tested successfully on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-28drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be ↵Stefan Reinauer
looking for. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-06Split the two usages of __ROMCC__:Myles Watson
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them." __PRE_RAM__ means "Use simpler versions of functions, and no device tree." There are probably some places where both are tested, but only one is needed. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-27Add few missing prototypes, and remove few unused (thus lonelly) variables.Maciej Pijanka
TODO - x86emu need (imo) some common header with prototypes at least - clog2, ulzma, hardwaremain prototypes added by this patch probably should be moved to some header too. - in src/devices/device_util.c prototype is before function because seems, it is used only within same file, if not it should be moved to debug section of prototypes in include/device/device.h Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-30Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):Uwe Hermann
- Implement ISA related support: - Initialize the RTC - Enable access to all BIOS regions (but _not_ write access to ROM) - Enable ISA (not EIO) support - Without the *_isa.c file, the Super I/O init is never performed - Improve IDE support: - Add config option to enable Ultra DMA/33 for each disk - Add config option to enable legacy IDE port access - Implement hard reset support - Implement USB controller support - Various code cleanups and improvements The code partially supports southbridges other than the 82371EB (but which are very similar), more complete support will follow. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Intel 82371EB: Some code simplifications (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-29Intel 82371EB: Add IDE init support.Uwe Hermann
In a mainboard's Config.lb file you can configure whether the primary and/or secondary IDE interfaces shall be enabled. Also, various fixups in the rest of the southbridge code, most notably the early SMBus code, plus some documentation improvements. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey_osgood@verizon.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Init for the Intel 82371EB southbridge: make all ROM/BIOS regionsUwe Hermann
accessible (but not writable), so that reading/loading a payload from that area can work (for instance). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,Uwe Hermann
as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1