| Age | Commit message (Expand) | Author |
|---|---|---|
| 2008-01-18 | Please bear with me - another rename checkin. This qualifies as trivial, no | Stefan Reinauer |
| 2007-11-30 | Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s): | Uwe Hermann |
| 2007-11-29 | Restructure/rename/comment a few 82371XX-related PCI IDs (trivial). | Uwe Hermann |
| 2007-10-24 | Ever wondered where those "setting incorrect section attributes for | Stefan Reinauer |
| 2007-06-03 | Intel 82371EB: Some code simplifications (trivial). | Uwe Hermann |
| 2007-05-29 | Intel 82371EB: Add IDE init support. | Uwe Hermann |
| 2007-05-27 | Init for the Intel 82371EB southbridge: make all ROM/BIOS regions | Uwe Hermann |
| 2007-05-03 | Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB, | Uwe Hermann |
| 2006-08-04 | final rename orgy. sorry for the inconvenience. This should fix it again | Stefan Reinauer |
| 2006-08-04 | ouch. it's 8_2_371. I'll fix it. This commit breaks compilation | Stefan Reinauer |
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index : coreboot | |
| Some coreboot project code with my work | vimacs |
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