coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-27	sb/intel/i82801ix: Use common early SPI code	Angel Pons
2020-06-22	sb/intel/i82801ix: Rename i82801ix_lpc_decode()	Angel Pons
2020-06-12	sb/intel/i82801ix: Use PCI bitwise ops	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-12-14	bootblock: Provide some common prototypes	Kyösti Mälkki
2019-10-28	nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support	Arthur Heymans
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-01-09	cpu/intel: Use the common code to initialize the romstage timestamps	Arthur Heymans
2017-11-23	sb/intel/i82801ix: fetch initial timestamp in bootblock	Arthur Heymans
2016-08-31	src/southbridge: Code formating	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2014-11-05	soutbridge/*/bootblock: Use pci_dev_t over device_t typedef	Edward O'Callaghan
2014-07-08	southbridge: Trivial - drop trailing blank lines at EOF	Edward O'Callaghan
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-27	intel/i82801ix: new southbridge, ICH9	Patrick Georgi