coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2020-01-14	sb/intel/common: Declare common smbus_base() and enable_smbus()	Kyösti Mälkki
2019-10-30	src/southbridge: change "unsigned" to "unsigned int"	Martin Roth
2019-10-14	sb/intel/i82801ix: Add common code to set up LPC IO decode ranges	Arthur Heymans
2019-08-21	southbridge/intel: Tidy up preprocessor and headers	Kyösti Mälkki
2019-07-10	intel/i82801ix: Rename smm_lock() prototype	Kyösti Mälkki
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2019-01-14	sb/intel: Use common RCBA MACROs	Peter Lemenkov
2019-01-06	Kconfig: Unify power-after-failure options	Nico Huber
2018-08-14	sb/intel/i82801[ij]x: use (more) RCBA register names instead of magic numbers	Stefan Tauner
2018-06-21	sb/intel/i82801xx: Use common RCBA MACROs	Arthur Heymans
2017-08-06	sb/intel/*: Use common SMBus functions	Arthur Heymans
2016-12-11	intel/gm45: Use romstage_handoff for S3	Kyösti Mälkki
2016-01-07	Correct some common spelling mistakes	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-07-12	Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()	Martin Roth
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-05-03	src/southbridge/intel/i82801ix: Add GPIO register locations	Timothy Pearson
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-08-11	i82801ix: Declare gen decode registers.	Vladimir Serbinenko
2013-10-01	qemu: q35: avoid address conflict	Gerd Hoffmann
2013-03-01	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	Paul Menzel
2012-11-27	intel/i82801ix: new southbridge, ICH9	Patrick Georgi