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coreboot
2560p
820g2
autoport-hsw
broadwell_refcode
e6230
e7240_bdw
haswell-mrc
hp820g1
hp9480m
mec1322
Some coreboot project code with my work
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path:
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src
/
southbridge
/
intel
/
lynxpoint
/
me_9.x.c
Age
Commit message (
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Author
2014-06-21
intel boards: Use acpi_is_wakeup_s3()
Kyösti Mälkki
2014-06-20
southbridge/intel/lynxpoint/me_9.x.c: Use IS_ENABLED macro
Edward O'Callaghan
2013-12-21
lynxpoint: me: Disable some verbose messages
Duncan Laurie
2013-12-21
lynxpoint: me: Support ICC clock enables message
Duncan Laurie
2013-12-21
lynxpoint: me: Allow for more than MKHI MEI messages
Duncan Laurie
2013-12-21
lynxpoint: Avoid any ME device communication in S3 path
Duncan Laurie
2013-12-21
lynxpoint me: add support for mbp clear wait in finalize step
Duncan Laurie
2013-12-21
Revert "lynxpoint: Move ME lock down to ramstage"
Duncan Laurie
2013-11-25
lynxpoint: Move ME lock down to ramstage
Duncan Laurie
2013-11-25
lynxpoint: Add missing ME MBP entries
Duncan Laurie
2013-03-22
x86: Unify arch/io.h and arch/romcc_io.h
Stefan Reinauer
2013-03-21
lynxpoint: update MBP give up routine
Aaron Durbin
2013-03-14
haswell: more ULT/LP support and minor tweaks
Duncan Laurie
2013-03-14
lynxpoint: ME to BIOS Payload Updates
Aaron Durbin
2013-03-14
haswell: remove explicit pcie config accesses
Aaron Durbin
2013-03-14
lynxpoint: Management Engine Updates
Aaron Durbin
2013-03-14
haswell: Add initial support for Haswell platforms
Aaron Durbin