coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-04-21	nb/intel/haswell: Add an option for where verstage starts	Arthur Heymans
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2018-11-07	sb/intel: Deduplicate vbnv_cmos_failed and rtc_init	Patrick Rudolph
2018-06-14	src: Get rid of device_t	Elyes HAOUAS
2017-10-22	security/vboot: Move vboot2 to security kconfig section	Philipp Deppenwiese
2017-09-20	vboot: reset vbnv in cmos when cmos failure occurs	Aaron Durbin
2017-09-20	southbridge/intel/lynxpoint: refactor rtc failure checking	Aaron Durbin
2017-07-16	southbridge/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-07-02	southbridge/intel/lynxpoint: Fix undefined behavior	Ryan Salsamendi
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2013-04-03	lynxpoint: Cosmetic cleanup	Stefan Reinauer
2013-04-01	lynxpoint: fix enable_pm1() function	Aaron Durbin
2013-03-22	Fix compilation of Intel LynxPoint based boards	Stefan Reinauer
2013-03-21	lynxpoint: Add power management helper functions	Duncan Laurie