coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-05-01	sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND register	Elyes HAOUAS
2020-04-04	src/southbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2019-12-19	src/southbridge: Remove unused <stdlib.h>	Elyes HAOUAS
2019-08-21	southbridge/intel: Tidy up preprocessor and headers	Kyösti Mälkki
2019-03-21	{northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()	Subrata Banik
2019-03-16	src: Drop unused 'include <device/pciexp.h>'	Elyes HAOUAS
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2019-03-01	device/pci: Fix PCI accessor headers	Kyösti Mälkki
2018-10-18	src/{sb/intel,mb/google/auron}: Don't use device_t	Elyes HAOUAS
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-02-15	x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer	Kevin Paul Herbert
2014-02-12	lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode	Duncan Laurie
2013-11-25	lynxpoint: Enable SerialIO clock in PCI mode	Duncan Laurie
2013-04-01	lynxpoint: Basic configuration of SerialIO devices	Duncan Laurie