coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-12-03	sb/intel/lynxpoint: Make the finalise handler common	Tristan Corrick
2018-06-14	src: Get rid of unneeded whitespace	Elyes HAOUAS
2018-06-14	src: Get rid of device_t	Elyes HAOUAS
2018-04-28	src/southbridge: Add spaces around '=='	Elyes HAOUAS
2017-07-16	southbridge/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2016-08-31	src/southbridge: Code formating	Elyes HAOUAS
2016-07-15	southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions	Aaron Durbin
2016-01-07	Correct some common spelling mistakes	Martin Roth
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-01-04	smihandler.c: Fix doxygen errors in southbridge_smi_handler	Martin Roth
2014-12-02	Replace hlt with halt()	Patrick Georgi
2014-07-04	intel/lynxpoint: Use separate SMI callback for USB XHCI routing	Duncan Laurie
2013-12-21	lynxpoint: Route all USB ports to XHCI in finalize step	Duncan Laurie
2013-12-21	lynxpoint: Move USB SMI sleep code to separate USB files	Duncan Laurie
2013-11-25	lynxpoint: Enable USB clock gating, late setup, and sleep prep	Duncan Laurie
2013-03-22	x86: Unify arch/io.h and arch/romcc_io.h	Stefan Reinauer
2013-03-21	haswell/lynxpoint: Use new PCH/PM helper functions	Duncan Laurie
2013-03-18	haswell: Use SMM Modules	Aaron Durbin
2013-03-14	haswell: remove GPIO60 memory reset gate on S3 transition	Duncan Laurie
2013-03-14	haswell: remove explicit pcie config accesses	Aaron Durbin
2013-03-14	haswell: Add initial support for Haswell platforms	Aaron Durbin