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2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05. This commit was submitted without its parent being submitted, resulting in coreboot not building. Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-11model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU. Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23432 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06sb/intel/common/firmware: Allow CONFIG_USE_ME_CLEANER on Kaby LakeNicola Corna
Some users have reported a successful boot with me_cleaner on Kaby Lake with OEM firmware: https://github.com/corna/me_cleaner/issues/3 It should work as well on coreboot. Change-Id: Ifc47f19deee5c39ca27b427c9406da7f6e3e9f15 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25507 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05sb/intel/bd82x6x: Let mainboard override SPI opmenuNico Huber
For some SPI chips (e.g. those with AAI writes), the default OPMENU definitions don't work well. Thus, provide an option to override the defaults in the devicetree. Writing the OPMENU now happens in ramstage instead of the SMM finalize handler. If you let coreboot call the finalize handler, nothing should change. If you call the handler from your payload, OTOH, the OPMENU might have been changed in between, so be careful what you lock. Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-28sb/intel/common: Add common code for SMM setup and smihandlerArthur Heymans
This moves the sandybridge both smm setup and smihandler code to a common place. Tested on Thinkpad X220, still boots, resume to and from S3 is fine so smihandler is still working fine. Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-08nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. GFXVTBAR/VTVC0BAR policy registers set to be consistent with proprietary vendor firmwares on hardware of same platform (2 different vendor firmwares compared, found to be identical). Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24983 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02sb/intel/common: Fix conflicting OIC register definitionNico Huber
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14mb/*/*/romstage.c: Clean up targets with i82801gxArthur Heymans
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-05sb/intel/i82801ix: Don't select HAVE_INTEL_FIRMWARE on Q35-QEMUArthur Heymans
The Qemu q35 target doesn't support or needs Intel Firmware blobs so it doesn't make sense to select that option on this hardware. The result of this change will be that when changing the ROM chip size, CBFS_SIZE will automatically fill the whole flash which is desirable in this case. Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23090 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-12-20intel/bd82x6x: Use generated ACPI PIRQTobias Diedrich
Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 (sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X. This generates the main ACPI _PRT table automatically based on the chipset registers. Tested on Intel NUC DCP847SKE with Linux 4.13.14: $ cat /proc/interrupts CPU0 CPU1 0: 23 0 IO-APIC 2-edge timer 8: 1 0 IO-APIC 8-edge rtc0 9: 0 0 IO-APIC 9-fasteoi acpi 19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1 23: 0 0 IO-APIC 23-fasteoi i801_smbus [...MSI and other interrupts skipped...] Log messages: ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6 ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4 ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4 ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8 ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1 Generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-20sb/intel/common: Automatically generate ACPI PIRQTobias Diedrich
Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34 (sb/intel/common: Add function to automatically generate ACPI PIRQ). This adds functionality to generate PIRQ ACPI tables automatically based on the chipset registers. Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific intel_common_map_pirq() function, an shared implementation of which is provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint chipsets. Example generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-10sb/intel/i82801jx: Hook up spi codeArthur Heymans
Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-10sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPIArthur Heymans
This introduces a Kconfig option to include common Intel SPI code. Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07sb/intel/i82371eb: Rework ACPI tablesKeith Hui
Rework ACPI tables based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. To be pulled in by DSDTs of mainboards using this southbridge. Disable on-the-fly generation of mainboard _CRS node. It is not working as it should and causes runtime errors when booting Linux. This node to be included in mainboard DSDTs in followup patches. Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07intel/bd82x6x: Fix a small mistake in DIR_ROUTETobias Diedrich
The register is 16-bits wide. If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten. See page 407ff on the Intel C216 datasheet, which says "Size: 16bits" with "Default: 3210h" for all DnnIR registers. This also makes sense given the register offsets: 3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W [3142h would be D30IR] 3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W 314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W 3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W [discontinuity in register addresses here] 315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W [315Eh would be D21IR] 3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-07intel/bd82x6x: Add missing IRQs in ACPI PIRQ link devicesTobias Diedrich
pch_pirq_init() sets all PIRQ links to route to irq 11. However in the ACPI data, on half the links irq 11 is missing. The other half is missing irq 10. This fixes a mostly cosmetic issue in the Linux messages: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15) ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11 ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15) Change-Id: I002147d702cacf54a233196932b30732f6a433b3 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-03sb/intel: Replace DTS2 with FLVLPatrick Rudolph
Replace the unused DTS2 field with FLVL (fan level). Required to use the fan level on all thinkpads to store and retrieve the current fan level. Possible additional use case is to modify the fan level from a SMI handler. Change-Id: I1ee5348d24b018ab1b61067813c1db63d6706c12 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22513 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-11-30acpi/tpm: remove non-existent IRQ for Infineon TPM chipMatt DeVillier
The Infineon TPM chip used on these platforms doesn't use an IRQ line; the Linux kernel has been patched to work around this, but better to remove it completely. Test: boot linux on google/wolf,lulu,cyan without tpm_tis.interrupts=0 kernel parameter, observe no abnormal delays in boot or resume from S3. Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-11-30acpi/tpm: update TPM preprocessor guardsMatt DeVillier
Replace '#ifdef ENABLE_TPM' with '#if IS_ENABLED(CONFIG_LPC_TPM)' for platforms which use a TPM on the LPC bus, so that the TPM ACPI code isn't included when the Kconfig option is deselected. Change-Id: Ia4c0d67dd3b044fe468002dff9eeb4f75f9934f9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-11-23sb/intel/i82801jx: Store initial timestamp in bootblockArthur Heymans
The function to fetch this timestamp is already present. Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23sb/intel/i82801ix: fetch initial timestamp in bootblockArthur Heymans
TESTED on Thinkpad x200 Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-03sb/intel/i82371eb: Consolidate bootblock.c logicKeith Hui
The southbridge bootblock entry point bootblock_southbridge_init() just calls i82371eb_enable_rom() which does all the work. Move all that code into bootblock_southbridge_init() and drop the second function. Plus combine the 3 lines that set 3 bits in XBCS into one. Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19sb/intel/bd82x6x: Add new USB currentsVagiz Trakhanov
These currents were found on Gigabyte GA-Z77-DS3H with vendor bios. Change-Id: I547c4ab3a2ce507d013ed527ab81291a916ce9b5 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-22sb/intel/bd82x6x: Revise flash ROM lockdown optionsNico Huber
The original options were named and described under the false assumption that the chipset lockdown would only be executed during S3 resume. Fix that. Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-09-22sb/intel/common/spi.c: Port to i82801gxArthur Heymans
Offsets are a little different. Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21113 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20vboot: reset vbnv in cmos when cmos failure occursAaron Durbin
There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20southbridge/intel/bd82x6x: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to early_pch_common.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I710d99551cfb6455244f66b47fcbecc790ae770f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20southbridge/intel/lynxpoint: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-19sb/intel/bd82x6x: Add awareness of ME's Alt Disable ModeNathaniel Roach
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable tells the ME to stop execution after BUP - disabling the 30 minute watchdog - but also "breaking" the ME. The ME reports opmode = 2. This means the ME will not respond when we wait for an acknowledgement about the DRAM being ready. The current code waits 5 seconds for a response, that in this case, never comes. If the ME is reporting opmode 2, don't delay or wait for a response from the ME. Tested on my X220, this patch fixed the five seconds before the payload executed. Verified using the timestamp patch. Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13sb/intel/bd82x6x: Add time-stamp around ME DRAM updateNathaniel Roach
Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-12sb/intel/i82801jx: Add smbus block operationsArthur Heymans
Change-Id: I1a84b4451efe25c1c3b0ce33ddbcb6ed06c29f9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-10sb/intel/common: Fix HAVE_DEBUG_SMBUSKyösti Mälkki
Failed to build with DEBUG_SMBUS=y, slave_bytes is not initialized until inb(). Change-Id: Ia53717756ed74bc797a9529e36fc6965d6872101 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21470 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-09sb/intel/common: Add HAVE_DEBUG_SMBUSKyösti Mälkki
Change-Id: Ifb1a1eff71968f31af9004ff00717f202d3ec29e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09sb/intel/common: Fix i2c block commandKyösti Mälkki
Coding style, sync implementation with SMBus counterpart. Change-Id: I75f24e2308de945fc03289636ae914bb87070838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09sb/intel/common: Tidy up SMBus block commandsKyösti Mälkki
I forgot to push these changes before merging commit 1b04aa2 sb/intel/common: Fix SMBus block commands Change-Id: I7217f8c0cc78f2161faf31a4c49e3e9515026d15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-06sb/intel/i82801jx: Use __packedJonathan Neuschäfer
__packed has been introduced in commit 6a00113de8 ("Rename __attribute__((packed)) --> __packed"). Use it. Change-Id: Ifd33129ae4fbe14c26ceeaaa88832ef994a32dfb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-30sb/intel/*: add option to lockdown chipset on normal boot pathBill XIE
On platforms with a PCH, some registers within host bridge should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). A function to perform such locking is implemented in src/northbridge/ intel/*/finalize.c, and is designed as the handler of an #SMI triggered with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only triggered during s3 resume, and not on normal boot path. This problem has beed discussed in https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html . This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/ intel/common/Kconfig is added to control the actual locking, which depends on several compatibility flags, including "HAVE_INTEL_CHIPSET_LOCKDOWN". In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint" have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected. The change is only well tested on Sandy Bridge, my Lenovo x230. Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-29sb/intel/bd82x6x: make hotplug map consistent to remapped portsBill XIE
"pcie_port_coalesce" will cause pcie being remapped under certain conditions, but flags within "pcie_hotplug_map" should be updated along with ports. Test on my lenovo t430s. Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21178 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-27sb/intel/*/nvs: Rename registerPatrick Rudolph
Rename register to match recent intel models. Required for Lenovo H8 to operate on all generations. Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-20util/me_cleaner: Pull the latest changes from upstreamNicola Corna
Relevant changes (commit 2e8761e): * Add an option to truncate the ME image file * Add full support for Skylake (ME 11) and following, including modules removal, truncation informations and partition relocation * Add two options to generate a shrinked ME image file and the corresponding descriptor with a modified flash layout * Update README.md * Bug fixes Also add a link to the usage guide in the Kconfig help. Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/20915 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-08-20sb/intel/common: Fix SMBus block commandsArthur Heymans
Clear LAST_BYTE flag at beginning of block commands. For reads, slave device determines in the message format how many bytes it has to transfer out, host firmware only dictates the maximum buffer length. Return SMBUS_ERROR if only partial message was received. For writes, return SMBUS_ERROR if length > 32. For writes, fix off-by-one error reading memory one byte past the buffer end. Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-19i82801dx/gx/ix/jx: Add low-memory backup for S3 pathKyösti Mälkki
SMM relocation code overwrite low memory owned by OS. Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19405 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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