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2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-02sb/intel/bd82x6x: Disable unused bridgesPatrick Rudolph
Disable unused bridges that are not marked as hot-plugable. Reduces idle power consumtion by ~200mWatt for each port. Tested on Lenovo T430. Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19818 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02sb/intel/bd82x6x/early_usb: Use register namePatrick Rudolph
Use register name instead of magic value. Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-31sb/lynxpoint: add missing USB port defsMatt DeVillier
Add device/address stubs for XHCI USB ports 7, 10-13. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19965 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-31sb/lynxpoint: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31sb/bd82x6x: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-24southbridge/intel: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-23sb/intel/common: Add common EC fw supportLijian Zhao
Add support to the Intel common firmware Kconfig and Makefile.inc to allow the embedded controller (EC) blob to be added to the final binary through ifdtool. TEST=Add ec.bin and enable in config, build is successful. Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-21sb/intel/bd82x6x/finalize: Lock ETR3 CF9GRPatrick Rudolph
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf" Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-20sb/intel/i82801ex: Remove unused codeArthur Heymans
Only board using this code was tyan s2735 which was removed in f76de841f1 "[REMOVAL] tyan/s2735" Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-19drivers/spi/spi_flash: Move flash ops to spi_flash_ops structureFurquan Shaikh
Define a new spi_flash_ops structure, move all spi flash operations to this structure and add a pointer to this structure in struct spi_flash. BUG=b:38330715 Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/spi_flash: Clean up SPI flash probeFurquan Shaikh
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it so that drivers can use it outside spi_flash.c. 2. Make southbridge intel spi driver use spi_flash_generic_probe if spi_is_multichip returns 0. 3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to provide specialized probe functions. With this change, the specialized spi flash probe functions are now associated with a particular spi ctrlr structure and no longer disconnected from the spi controller. BUG=b:38330715 Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-19drivers/spi/spi_flash: Pass in spi_slave structure as const to probe functionsFurquan Shaikh
Pointer to spi_slave structure can be passed in as const to spi flash probe functions since the probe functions do not need to modify the slave properties. BUG=b:38330715 Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19707 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05drivers/spi: Re-factor spi_crop_chunkFurquan Shaikh
spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-05-05sb/intel/bd82x6x/bootblock: Use register namePatrick Rudolph
Use defines instead of magic values. No functional change. Change-Id: Idc90f254d7713f96a6e8b0389e34d860f461d9d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-05sb/intel/bd82x6x/finalize: Use register namePatrick Rudolph
Use register name instead of hex values. No functional change. Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-01nb/intel/sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I97c3402ac055991350732e55b0dda042b426c080 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01nb/intel/nehalem/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-01nb/intel/fsp_sandybridge/gma: Set up OpRegion in nb codePatrick Rudolph
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19307 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-27i82801gx: Enable PCI-to-PCI bridgeKyösti Mälkki
Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. Since the LPC function claims the resources for IOAPIC, ROM and low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI configuration will not overlap those regions and does not hide the resources mentioned in the original comment. The bridge was disable in the following commit [1] commit a8e1168064b34b46494b58480411a11bc98340f6 Author: Stefan Reinauer <stepan@coresystems.de> Date: Wed Mar 11 14:54:18 2009 +0000 This patch contains some significant updates to the i82801gx component and will be required for a series of later patches. Roughly it contains: but unfortunately it was not noted which system this caused problems with. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6 Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/2706 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-11sb/intel/i82801gx: Add i2c_block_read to smbus.hArthur Heymans
Using i2c_block_read speeds up reading SPD four to fivefold compared to sequential byte read. TESTED on Intel D945GCLF. Change-Id: I6d768a2ba128329168f26445a4fca6921c0c8642 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18927 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-22southbridge/intel/i82801gx: Fix problems found by checkpatch.plArthur Heymans
Change-Id: Iddc67e7c126ce19429afc24b021e385353564cb8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18705 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-19sb/intel/common/firmware: Add Intel ME/TXE firmware checkNicola Corna
Ensure that the provided ME/TXE firmware is valid, using the check capabilities of me_cleaner. me_cleaner checks that the fundamental partition is available and it has a correct signature. The checks performed by me_cleaner aren't exhaustive, but they should find at least whether the user has provided an empty or corrupted firmware. me_cleaner has been tested on all the ME (6-11.6) and TXE (1-3) firmwares available here [1], and it hasn't reported any false positive. [1] http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html Change-Id: Ie6ea3b4e637dca4097b9377bd0507e84c4e8f687 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18768 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-02-23lynxpoint bd82x6x: Enable PCI-to-PCI bridgeKyösti Mälkki
Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. It was previously argumented this is copy-paste and never known to be required for these more recent platforms: https://review.coreboot.org/#/c/2706/ Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18330 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20lynxpoint/broadwell: fix PCH power optimizerMatt DeVillier
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC Configuration; offset 0x33c8) causes pre-OS display init to fail on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP driver is run after the register is set. A re-examination of Intel's reference code reveals that bit 7 should be set for the LP PCH, and bit 27 for non-LP, but not both simultaneously. The previous workaround was to disable the entire power optimizer section via a Kconfig option, which isn't ideal. Test: unset bit 27 of PMSYNC_CFG and boot google/lulu, observe functional pre-OS video output Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18385 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"Matt DeVillier
We've been able to narrow down the problem to a single register/ single bit, so revert this commit and address the problem in a follow-on commit. This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db. Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18384 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-08southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BINAaron Durbin
The apollolake boards don't have an me.bin proper, but they still have descriptor regions which need to be locked down. Therefore, remove the restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE. BUG=chrome-os-partner:62177 TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE. Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18304 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-04sb/intel/common: Hook up me_cleanerNicola Corna
The me_cleaner option is available on multiple platforms: * Sandy and Ivy Bridge (well tested by multiple users). * Skylake and Braswell (tested). * Haswell, Broadwell and Bay Trail (untested). The untested platforms have been included anyways because all the firmwares are very similar and Intel ME/TXE probably behaves in the same way. Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18206 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-12sb/intel/ibexpeak: Update debug code to match other chipsMartin Roth
Other chips dump tco_status here if it wasn't handled, which makes sense. tco_sts can't be zero here, because the call would have already returned if it were. Also, dump_tco_status wouldn't print anything if tco_sts were zero. This will still only print the debug information if DEBUG_SMI is enabled in Kconfig, so in general, this change won't have much of an effect on anything. Found-by: Coverity Scan #1229598 Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18101 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12sb/intel/fsp_rangeley: Fix NULL check in gpio.cMartin Roth
This should always have been an and, not an or. The only way this would happen is if no GPIOs were getting configured, so we shouldn't ever have a NULL here, but if we did, GPIOs would be randomly configured, which would have 'interesting' results. Found-by: Coverity Scan #1229633 & 1229632 Change-Id: If123372658383f84279738e1186425beba3208ca Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12fsp 1.0 systems: Check for NULL when saving HobListPtrMartin Roth
Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18092 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-10intel/i82801dx: Support 2MiB FWH partKyösti Mälkki
Default setting of southbridge assigned 1MiB of memory for FWH ID 0, while 2MiB is commercially available. Only remap IDs when large ROM is requested in case some board uses multiple FWH parts. Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17918 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-06sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03sb/intel/common/gpio: Support ICH9M and priorPatrick Rudolph
Write gpio level twice to make sure the level is set after pins have been configred as GPIO and to minimize glitches on newer hardware. Required to set correct GPIO layout on T500. Tested on T500. Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18012 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
2016-12-23spi: Get rid of SPI_ATOMIC_SEQUENCINGFurquan Shaikh
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-18intel/i82801ix: Add HAVE_INTEL_FIRMWAREKyösti Mälkki
Select this to provide menu in menuconfig to add flash descriptor file. ME or GbE firmwares themselves are not required, but integrated NIC MAC and SPI configuration fields are still useful. Change-Id: I14b86e2f38ec39924d2cbf0932d82f66ed356a03 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17805 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-11intel/i945: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Scratchpad register was read too late in ramstage so acpi_is_wakeup_s3() did not evaluate correctly. This fixes low memory corruption at 0x1000-0x102c and the lack of coreboot tables (util/cbmem not working) after S3 resume. This also fixes console log from reporting early in ramstage "Normal boot" while on "S3 resume" path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17675 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11intel/gm45: Use romstage_handoff for S3Kyösti Mälkki
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11x86 SMM: Fix use with RELOCATABLE_RAMSTAGEKyösti Mälkki
The value for _size was not evaluated correctly if ramstage is relocated, make the calculation runtime. While touching it, move symbol declarations to header file. Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-10intel 82801dx/gx/ix: Commit SMM relocation code to DRAMKyösti Mälkki
Make sure relocation code reaches DRAM before issuing any SMIs. Snooping and cache coherency may have undefined behaviour as CPUs do not have uniform MTRR layout yet. Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17712 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17655 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-08sb/intel/bd82x6x: Add TCO_Lock in finalize stepDennis Wassenberg
CHIPSEC found that the TCO_Lock was not set. This is used to prevent changing the TCO_EN bit. Change-Id: I42364dbef2511e656662566cf94591e76c6847ed Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Reviewed-on: https://review.coreboot.org/17351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07PCI ops: MMCONF_SUPPORT_DEFAULT is requiredKyösti Mälkki
Doing PCI config operations via MMIO window by default is a requirement, if supported by the platform. This means chipset or CPU code must enable MMCONF operations early in bootblock already, or before platform-specific romstage entry. Platforms are allowed to have NO_MMCONF_SUPPORT only in the case it is actually not implemented in the silicon. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06spi_flash: Make a deep copy of spi_slave structureFurquan Shaikh
Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
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