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2012-04-04Add support for Intel Panther Point PCHStefan Reinauer
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-24i82801gx: Support power-on-after-power-fail betterPatrick Georgi
Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-24i82801gx: Use CMOS variable if available for power-on on power failurePatrick Georgi
We used a hard coded value for some reason. Don't do that, but use CMOS instead. Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17intel/i82801cx: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/662 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17intel/i82801ex: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/664 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17intel/sch: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/665 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-02-17Avoid ../../.. paths in ASL filesPatrick Georgi
The current directory is always part of the search path of cpp when using #include "..." Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/648 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17Remove whitespace.Patrick Georgi
Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17intel/82801dx: Move HAVE_HARD_RESET to southbridgePatrick Georgi
No in-tree 82801dx-using board has it not selected, so move selection from boards to southbridge. Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/655 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-02i3100: configure pci irqsSven Schnelle
without it, you can't boot from PCI devices like scsi controllers which require an interrupt set. So preconfigure all pci devices. Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/603 Tested-by: build bot (Jenkins)
2012-01-31i3100: add sata_ports_implemented optionSven Schnelle
BIOS needs to set the bit mask which ports are iplemented on the board. Without setting this option, seabios fails to boot from SATA. Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/601 Tested-by: build bot (Jenkins)
2012-01-31i3100: Add init sequenceSven Schnelle
i3100 misses the magic SATA init sequence, which makes all requests fail. Captured from the vendor BIOS, which writes those bits on all configurations. Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/600 Tested-by: build bot (Jenkins)
2012-01-10Add missing HAVE_HARD_RESETSven Schnelle
Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/531 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-12-02i3100: Add HAVE_HARD_RESETSven Schnelle
and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-31Fix usb debug dongle supportSven Schnelle
- move enable_usbdebug() declaration to usbdebug.h - reinitialize debug driver in ramstage, as copying the data structure from romstage doesn't work right now. This way of copying data from romstage to ramstage is really board/cpu specific, and is likely to break often. So don't do it. Change-Id: I394678ded6679c1803e29eb691b926182bdcab68 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/355 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27i82801gx: Fix port status in AHCI modeSven Schnelle
The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/340 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25i82801gx: Add setting for C4onC3 modeSven Schnelle
If this bit is set, ich7 will enter C4 mode if possible instead of C3. See ich7 specification (LPC controller, Power management control registers) for more details. Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25i82801gx: Add write and read/write block functionsSven Schnelle
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-23i82801gx: Don't set I/O base address to static valueSven Schnelle
Doing it this way will break all subsequent smbus calls, because the smbus code still uses res->base, which points to the old base address. Fix this by allocating a proper resource. Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/325 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-10-21sch: strip quotes around cmc.bin filenamePatrick Georgi
This was mentioned several times already, how about we get it in? It avoids cbfstool to fail because path/to/"file" doesn't work. Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/305 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-20i82801dx: Replace romstage printk'sKyösti Mälkki
Patch is required to compile this with romcc. Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/291 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/276 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-21Use ACPI text fields consistently with all other boardsStefan Reinauer
LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 Reviewed-on: http://review.coreboot.org/224 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-12Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methodsTobias Diedrich
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29i82801gx: read RTC status register to prevent IRQ stormSven Schnelle
My Thinkpad appeared dead. After investigation, it turned out that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI handler didn't read the status register, so it was triggered again. This is a really nasty situation, as it means you have to dissemble your Notebook just to unplug the RTC battery. Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/67 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/34 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/33 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-07i82801gx: enable ACPI during S3 resumeSven Schnelle
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the Host OS is assuming that ACPI is enabled. Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/7 Tested-by: build bot (Jenkins)
2011-06-07SMM: add defines for APM_CNT registerSven Schnelle
in the current code, the defines for the APM_CNT (0xb2) register are duplicated in almost every place where it is used. define those values in cpu/x86/smm.h, and only include this file. And while at it, fixup whitespace. Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/4 Tested-by: build bot (Jenkins)
2011-06-06SMM: add mainboard_apm_cnt() callbackSven Schnelle
motherboards can use this hook to get notified if someone writes to the APM_CNT port (0xb2). If the hook returns 1, the chipset specific hook is also skipped. Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/3 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-05-03i82801gx: enable SPI prefetchingSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Fix compilation of all i82371eb boards when ACPI tables aren't generatedIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01ICH7: Fix register naming errorSven Schnelle
There's an off-by-one error in the ACPI GP_LVL declaration: it declares GL00 with a bit count of 6, and continues with GP07 afterwards. This should be GP06, as the first bitfield covers GP00-GP05. While at it, change it to GP00-GP05, as right now GL00 isn't used, and single bitfield are more usable here. Also adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functionsPatrick Georgi
This is so that boards can determine them on runtime based on hardware properties, if so desired. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-30Inverse two arguments of cbfs-files-y and adapts its users (one of which ↵Patrick Georgi
already used the new order) This is in reponse to feedback that the original setup was too complicated. New cbfs-files-y behaviour: cbfs-files-y contains the names of files as they appear in CBFS. The arguments describe the on-filesystem name, the type and (optionally) the position. Example: cbfs-files-y += foo foo-file := bar foo-type := splashscreen foo-position := 0xffff8000 This configures a CBFS file called "foo" that is marked "splashscreen", located at 0xffff8000 in flash and contains the data of the file "bar" in the filesystem (either in the current directory, ie. where the corresponding Makefile.inc resides, or if that doesn't exist, relative to the toplevel directory). Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27Intel SCH: make state machine binary selection available in Kconfig for now.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Fix a few whitespace and coding style issues.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18A couple of Poulsbo fixes:Patrick Georgi
- Don't include cmc.bin to the build. It's required, but we don't ship it - mptable's API changes a bit. Adapt. - Fix ACPI for new iasl versions with improved code validation Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
which uses it. Compiles, but not boot tested lately. Many things missing (eg. SMM support, proper ACPI, ...) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-09Merge enable_rom.c files into bootblock.c files.Uwe Hermann
All southbridges using TINY_BOOTBLOCK have a bootblock.c files which simply includes an enable_rom.c files. As discussed on the mailing list, drop the enable_rom.c file by merging it into bootblock.c. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08Tobias Diedrich wrote:Tobias Diedrich
> Definitively a iasl problem, it can't even disassemble it's own > output back to something equivalent to the input file. > It seems to be generating Bytecode for the Add where it shouldn't. Here is a solution using the SSDT. Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently. Abuild-tested. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08first round name simplification. drop the <component>_ prefix.stepan
the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the <componentname>_ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07Get rid of some unneeded function prototypes in romstage.c files.Uwe Hermann
Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-29Tobias Diedrich wrote:Tobias Diedrich
> Stefan Reinauer wrote: > > The specified IO port is most likely wrong. As the comment mentions, the > > SSDT is a good place for that. A preprocessor define used both in the > > CPU init code and in the asl would solve the problem without an SSDT. > > For some info on CPU SSDT creation on intel check out > > src/cpu/intel/speedstep/acpi.c > > The IO port is ok (and I wrote the comment myself ;)): > DEFAULT_PMBASE is 0xe400 > PCNTRL reg offset is 0x10 > > Using the preprocessor will probably work too if iasl can do simple > arithmetic (likely yes), I'll look into that. BTW, my first idea was to use an acpi method that looks up pmbase in the pci cfg space, but when I define a method like this: Method(TEST, 2) { Return (Add(Arg0, Arg1)) } I get: |build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0, |0x01, TEST(0xe400, 0x10), 0x06) {} |Error 4096 - syntax error, unexpected PARSEOP_NAMESEG, |expecting ')' ^ While using the builtin Add() directly works. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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