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2019-05-16nb/intel/sandybridge: Move DMI init codePatrick Rudolph
Move the DMI initialization code to northbridge folder. Leave southbridge specific settings in bd82x6x folder and call it from northbridge code. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-16sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcrosPatrick Rudolph
Use RCBA and DMIBAR macros to get rid of DEFAULT_RCBA and DEFAULT_DMIBAR. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-16sb/intel/sandybridge/early_pch: Make DMI init more readablePatrick Rudolph
Add a few comments and use known register values. Based on the "2nd Generation Intel® Core™ Processor Family Mobile" datasheet and the existing serialice trace. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to GNU/Linux. Change-Id: I404515b77a22324f55581f117d79630be4ba64dd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32071 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15src/southbridge: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: If358e221021466f0058bfc84a322750b34a36d5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-13i82801gx/bootblock: Use macro instead of magic numberElyes HAOUAS
Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macroElyes HAOUAS
Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-10sb/bd82x6x: Don't rewrite over BCTRLElyes HAOUAS
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done. Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10sb/i82801gx: Don't rewrite over BCTRLElyes HAOUAS
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx (see ICH7 Family Datasheet page 355). The write on that register is already done some lines above. So remove wrong register name and the wrong code line. Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10nb/intel/i945: Use macro instead of magic numberElyes HAOUAS
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10sb/i82801gx: Remove duplicated 'define PMBASE'Elyes HAOUAS
Change-Id: If08bea821043bc8e661bf5327f4fe2cef3a65be8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07sb/intel/bd82x6x: Fix flashconsole after lockdownDan Elkouby
SMM final locks the SPI BAR, which causes flashconsole to hang. Re-init it like SMM does with CONFIG_SPI_FLASH_SMM. Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07sb/{ICH7,NM10,PCH}: Use common watchdog_off functionElyes HAOUAS
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian
2019-05-06Fix code that would trip -Wtype-limitsJulius Werner
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06sb/intel/bd82x6x: Use common/rcba.hPatrick Rudolph
Make use of: * southbridge/intel/common/rcba.h * southbridge/intel/common/pmbase.c * defines in pch.h Get rid of dependency to DEFAULT_RCBA. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32066 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03{soc, southbridge} : Correct typo in commentFrans Hendriks
BUG=N/A TEST=N/A Change-Id: I1b207e0b77bac8860ba7501378297c1f3604141c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32453 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-29sb/intel/bd82x6x: Use system_reset()Elyes HAOUAS
Use already defined system_reset() function. Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-25src/southbridge/intel: Remove unused variablesElyes HAOUAS
Change-Id: I3b5092aa076b9693f78c86ffb9b99805696bb0bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-23sb/intel/bd82x6x: fix linking for non-native raminit caseMatt DeVillier
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x] moved early_pch_init() to the southbridge, but failed to include early_pch.c for the non-native raminit case, which now fails to link. As all boards default to native raminit, this was missed by the autobuilder. Adjust early_pch.c to be compiled regardles of ram init type used Test: build/boot google/stout with MRC ram init selected Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23sb/intel/lynxpoint: Enable LPC/SIO setup in bootblockArthur Heymans
This allows for serial console during the bootblock and enables console in general for the bootblock. Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23nb/intel/sandybridge: Drop pch.h from sandybridge.hPatrick Rudolph
Include pch.h in the source files instead in sandybridge.h. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-23sb/intel/i82801gx/lpc: Use {read,write}_pmbase32 and lpc_get_pmbaseElyes HAOUAS
Also use macros instead of magic numbers. Change-Id: I00bd687c487894c72d4e4363774dbcdfaf62dd54 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-21nb/intel/haswell: Add an option for where verstage startsArthur Heymans
Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-18nb/intel/sandybridge: Move southbridge code to bd82x6xPatrick Rudolph
Move the southbridge code to bd82x6x folder similar to the lynxpoint implementation. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-16sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Tested on Lenovo T520 (Intel Sandy Bridge) with Change I8afc9f966033f45823f5dfde279e0f66de165e93 applied as well. Still boots to OS, no errors visible in dmesg and S3 resume is working. Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-16sb/intel/i82801ix: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I618d4c25adb0d2b9bbd59a3b3b84beac78db1916 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-13sb/intel/common: Fix config name in a commentNico Huber
This sneaked in after we made unknown arguments to CONFIG() an error. Change-Id: Ia1de78ce1d3277c7b094c3283455f4b56f3a3fbb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32314 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Tested on Thinkpad X60. Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-13sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I87ac56e4ba1fb83761786d5f32a0fc308ee9718a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32039 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIBPatrick Rudolph
Use common code to detect ACPI S3. Untested. Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-13sb/intel/common: Add common detect_s3_resumePatrick Rudolph
Add a common detect_s3_resume function. Will be used by other southbridge code. TODO: Merge with soc/intel/common/*/pmclib Tested on Lenovo T520 (Intel Sandy Bridge) with Change I283a841575430f2f179997db8d2f08fa3978a0bb applied as well. Still boots to OS, no errors visible in dmesg and S3 resume is working. Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-07sb/intel/{common,i82801dx}: Improve TCO debug codeJacob Garber
Report unhandled TCO bits (previously dead code). This finishes the work done in 3e3b858 (sb/intel/ibexpeak: Update debug code to match other chips). Found-by: Coverity Scan, CID 1229598 (DEADCODE) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32179 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-27Move calls to quick_ram_check() before CBMEM initKyösti Mälkki
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-25sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()Kyösti Mälkki
Change-Id: Ia7a3eb2e29eb245c0e70abc23c2139aebc07cbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-21sb/intel/lynxpoint: Remove PCI bridge functionKyösti Mälkki
Legacy PCI-to-PCI (parallel) bridge 0:1e.0 is no longer supported in these SKUs. Change-Id: I954ee9cf8228c6352743cae968a0dd665865496c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-21{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()Subrata Banik
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well. Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-21{northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik
This patch removes local definitions of sub_system function and make use of common function pci_dev_set_subsystem(). Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: David Guckian Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19src/southbridge/intel/i82801gx/pcie.c: Correct NULL checkJacob Garber
Check if `pcie_dev` is NULL instead of `dev`. This was flagged as REVERSE_INULL during a Coverity scan, but is a simple typo. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Idc40574b9341d1b10cb2136cbc1a865efa3ab3ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/31866 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-16src: Drop unused 'include <device/pciexp.h>'Elyes HAOUAS
Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-16drivers/intel/fsp1_0: Deduplicate codePatrick Rudolph
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0. Allows to have a common entry after FSP-M. Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-03-14Remove leftover filesKyösti Mälkki
Change-Id: I7fa27a2cbc73b4acae41373a51f600f32b9002bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-14sb/intel/i82801gx: Remove unused include <arch/acpi.h>Elyes HAOUAS
Change-Id: I13b751ba4826f4fff86ffb6e00967192aab96d87 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-13{mb,nb/pineview}/*.asl: Remove unneeded include i82801gx.hElyes HAOUAS
Change-Id: I1a0eed712e489b0fb63a7b650151646a56852d76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30321 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12src: Drop unused 'include <arch/acpigen.h>'Elyes HAOUAS
Use <arch/acpi.h> when appropriate. Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 13:54:55 +0000