| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-04-20 | pci1x2x: remove latency/bridge control/cacheline size settings | Sven Schnelle |
| 2011-04-20 | pci1x2x: use devicetree register configuration | Sven Schnelle |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |