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2017-07-25sb/intel/i82801jx: Add Interrupt pin and routing RCBA offsets macrosArthur Heymans
Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-25sb/intel/i82801jx: Route all PIRQ to INT11Arthur Heymans
Interrupt 11 is not used by legacy devices and so can always be used for PCI interrupts. Full legacy IRQ routing is complicated and hard to get right. Change-Id: I6c718f4b9fb91ffcc4a136120581a4fcd7ec7231 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-25sb/intel/common/gpio: Only set one bit at timePatrick Rudolph
Make sure to set only one bit instead of arbitrary bits set in argument. Change-Id: I39426193d15d8581f79bc2a45c0edb53b19a2cd3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24sb/intel/i82801jx: Generate default fadt and madtArthur Heymans
Function copied from i82801gx with offsets fixed for i82801lx. Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23sb/intel/i82801jx: Add function to detect s3 resumeArthur Heymans
File copied from i82801gx. Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-23sb/intel/i82801jx: Add addition IO resourcesArthur Heymans
Adapted from i82801gx. Change-Id: I9108a45135908b7c4e74e9df3bb8f89f55893299 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21I82801JX: Add IS_ENABLED around config optionsMartin Roth
This chipset was just added and had a few places that needed to be fixed. Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20684 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-21sb/intel/i82801jx: Add correct PCI ids and change namesArthur Heymans
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21sb/intel/i82801jx: Copy i82801ixArthur Heymans
Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-18sb/amd/cs5536: Remove includes of C filesMartin Roth
The romstage for CS5536 platforms were including early_smbus.c and early_setup.c. Build these into romstage from the makefile, and remove the #includes. Add a Kconfig option for platforms that do not use the early smbus code. Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-17AGESA: Add guard for acpi_get_sleep_type()Kyösti Mälkki
With EARLY_CBMEM_INIT, this is defined from ACPI layer instead for ENV_RAMSTAGE. Change-Id: Ia9c1be4d3acaa0fa8827350558e6578c39b71602 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-16southbridge/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-13src/southbridge: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12binaryPI: Drop non-soc stoneyridge treesKyösti Mälkki
These sources are no longer part of build-tests and transition to soc/ appears to be completed. Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-10southbridge/intel/lynxpoint: Fix undefined behaviorRyan Salsamendi
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep, and source inspection. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-07-06sb/intel/i82870: Add whitespace around '<<'Elyes HAOUAS
Change-Id: Ic8b0e6404a3f90312f7d2d3b6c367b0a1d9ec6e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-07-06sb/intel/ibexpeak: Add whitespace around '<<'Elyes HAOUAS
Change-Id: Ib3a69f45b48c19c61b12a992b23dad1693bf5f9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-06sb/intel/lynxpoint: Add whitespace around '<<'Elyes HAOUAS
Change-Id: I1b2a16e8eb70819c72efd50f30a57f3687f31bb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-06sb/intel/i82801gx: Add whitespace around '<<'Elyes HAOUAS
Change-Id: I8ea8fdb031c09aac9ed4a0705c3204f87aadb565 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-03southbridge/intel/lynxpoint: Fix undefined behaviorRyan Salsamendi
Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that is not aligned to the size of access is undefined behavior. Change-Id: Ia3c95e36e8b7f88ed69d5339e299c40934cb87da Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-02southbridge/intel/lynxpoint: Fix undefined behaviorRyan Salsamendi
Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-30southbridge/amd: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-06-27sis/sis966: Clean up sata.cStefan Reinauer
Wow, this one is disliked by clang for the empty for() loop, but looking at the file just makes my eyes bleed a little bit. I remember the circumstances under which we let this code go in. It was supposed to save contributions from a vendor, but that never worked out. Just to keep the little chunks down, here's an indent run and some of the cruft removed that doesn't actually contribute to functionality in any way. Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27sb/intel/bd82x6x: Fill in acpi_namePatrick Rudolph
Fill in acpi_name to return proper ACPI names. To be used with SSDT generators. The ACPI names have to match those already used in ASL code. By providing the ACPI name it can be retrieved by the acpi_device_name() method and doesn't need to be hardcoded in SSDT generators any more. HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl. LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl. RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl. SATA is defined in sb/intel/bd82x6x/acpi/sata.asl. SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl. EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl. XHC is defined in sb/intel/bd82x6x/acpi/usb.asl. Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-22sb/amd/rs780/gfx.c: Add brackets around macroElyes HAOUAS
Code checked manually Change-Id: I5a9596328c028d570303e9390c0133b19b97d683 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/20259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-16southbridge/bd82x6x - add GNVS var for trackpad IRQMatt DeVillier
Add a GNVS variable to store trackpad IRQ for google/parrot, so that both SNB and IVB variants can be built with the same config Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-16sb/intel/common/firmware: Keep CHECK_ME disabled by defaultNaresh G Solanki
While building poppy board, build failed with following error message: Writing new image to build/coreboot.pre.new mv build/coreboot.pre.new build/coreboot.pre util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null This image does not contains a ME/TXE firmware NR = 0) make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55: add_intel_firmware] Error 1 Hence keeping CHECK_ME unset by default. TEST=Succesfully built coreboot for Poppy & booted to OS. Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-15Revert "sb/intel/bd82x6x: Disable unused bridges"Nico Huber
This reverts commit f4835a85c0e851d13bcfed53a23f495caeefe8e2. It completely ignores port coalescing and breaks enumeration in many cases. The code reused to disable and hide the root ports was never meant to be called that way. The same effect of power saving can likely be achieved by clock gating unused ports after enumeration without further, error-prone function hiding. Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-07spi: Remove unused/unnecessary spi_init function definitionsFurquan Shaikh
Remove spi_init definitions which: 1. Do nothing 2. Set static global variables to 0 Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20039 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-02sb/intel/bd82x6x: Disable unused bridgesPatrick Rudolph
Disable unused bridges that are not marked as hot-plugable. Reduces idle power consumtion by ~200mWatt for each port. Tested on Lenovo T430. Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19818 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02sb/intel/bd82x6x/early_usb: Use register namePatrick Rudolph
Use register name instead of magic value. Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-31sb/lynxpoint: add missing USB port defsMatt DeVillier
Add device/address stubs for XHCI USB ports 7, 10-13. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19965 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-31sb/lynxpoint: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-31sb/bd82x6x: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-27CBMEM: Clarify CBMEM_TOP_BACKUP function usageKyösti Mälkki
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-24southbridge/amd: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I2a789cff40fb0e6bd6d84565531d847afb3f8bed Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-24southbridge/intel: Move spi driver to use spi_bus_mapFurquan Shaikh
This is in preparation to get rid of the strong spi_setup_slave implemented by different platforms. BUG=b:38430839 Change-Id: I23c1108c85532b7346ff7e0adb0ac90dbf2bb2cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-23sb/intel/common: Add common EC fw supportLijian Zhao
Add support to the Intel common firmware Kconfig and Makefile.inc to allow the embedded controller (EC) blob to be added to the final binary through ifdtool. TEST=Add ec.bin and enable in config, build is successful. Change-Id: Ib14732b4d263dde4770bf26b055c005de2540338 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-22sb/via/k8t890: Clean up CONFIG_VGA usageNico Huber
Remove guards and let the linker take care of it. Change-Id: I96ad8002845082816153ca5762543768998a5619 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-21sb/intel/bd82x6x/finalize: Lock ETR3 CF9GRPatrick Rudolph
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf" Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-20sb/intel/i82801ex: Remove unused codeArthur Heymans
Only board using this code was tyan s2735 which was removed in f76de841f1 "[REMOVAL] tyan/s2735" Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-19drivers/spi/spi_flash: Move flash ops to spi_flash_ops structureFurquan Shaikh
Define a new spi_flash_ops structure, move all spi flash operations to this structure and add a pointer to this structure in struct spi_flash. BUG=b:38330715 Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/spi_flash: Clean up SPI flash probeFurquan Shaikh
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it so that drivers can use it outside spi_flash.c. 2. Make southbridge intel spi driver use spi_flash_generic_probe if spi_is_multichip returns 0. 3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to provide specialized probe functions. With this change, the specialized spi flash probe functions are now associated with a particular spi ctrlr structure and no longer disconnected from the spi controller. BUG=b:38330715 Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-19drivers/spi/spi_flash: Pass in spi_slave structure as const to probe functionsFurquan Shaikh
Pointer to spi_slave structure can be passed in as const to spi flash probe functions since the probe functions do not need to modify the slave properties. BUG=b:38330715 Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19707 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18AGESA: Fix UMA calculationsKyösti Mälkki
Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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