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Use of device_t has been abandoned in ramstage.
Change-Id: I661b2435d9f0306b246a3e89aac24eb30c959085
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: I5c18fdc24bd0432f6b7a1131af68c792d377c3ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use of device_t has been abandoned in ramstage.
Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add an lpc_acpi_name function to report its namespace as "LIBR"
rather than some fallback value which seems to vary. This repair
is required for the LPC TPM device to register its presence
without blowing up the table and preventing the payload from
seeing the SATA device.
Before change (but after other similar change to PCI0), the
TPM device reported itself as:
\_SB.PCI0.LPC0.TPM
After change, the TPM device reports as:
\_SB.PCI0.LIBR.TPM
which is consistent with the tables AGESA generates.
Change-Id: Ifa3a0e386cc00062855331e5f9d1c00d6541c238
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ia9d884d7247f0cc3a175de31649d0163c69f1299
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26035
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ic43b5ddaa395658ab7c34cdd004516884a20b005
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Fix regression after commit
7f5efd9 intel/bd82x6x: Use generated ACPI PIRQ
The call to inject generated PIRQ entry was not added when
the static entries as default_irq_route.asl file was removed
from boards using intel/nehalem southbridge.
Change-Id: I8097c1ab729d1eb91a6d547ef13948c1e21eca10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/25965
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id1bc0c88aeecc3f1d12964346326e5b087a2985e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25880
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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scan-build from Clang 4.0.1-3 from Debian Sid/unstable warns about the
issue below.
```
CC ramstage/southbridge/amd/cimx/sb800/lpc.o
src/southbridge/amd/cimx/sb800/lpc.c:102:6: warning: Value stored to 'end' is never read
end = resource_end(res);
^ ~~~~~~~~~~~~~~~~~
1 warning generated.
```
The variable is only used in the commented out print statement. So,
remove the unused variable, and directly use the value directly in the
print statement.
Change-Id: I3f759f6361ffeb07980cb10e17930e11d738a6a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I190d41816eef2a5b27a9026ed3d3c822eee8b42b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I94a87d631c9336b861523592ff217fe823436b36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: If4f3d3ed43fca1bff52ea99cc3eab29beb4e2a08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ic81601cef841076a7548ccb3bdf0ed1b5420873e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Instead of writing out '__attribute__((weak))' use a shorter form.
Change-Id: If418a1d55052780077febd2d8f2089021f414b91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05.
This commit was submitted without its parent being submitted,
resulting in coreboot not building.
Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch adds a few southbridge calls needed for parallel MP init.
Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.
Tested on Thinkpad X220, shaves of ~30ms on a 2 core, 4 threads CPU.
Change-Id: Iacd7bfedfccbc09057e1b7ca3bd03d44a888871d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23432
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's a standard function.
Change-Id: I039cce2dfc4e168804eb7d12b76a29af712ac7a1
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some users have reported a successful boot with me_cleaner on Kaby Lake
with OEM firmware:
https://github.com/corna/me_cleaner/issues/3
It should work as well on coreboot.
Change-Id: Ifc47f19deee5c39ca27b427c9406da7f6e3e9f15
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25507
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For some SPI chips (e.g. those with AAI writes), the default OPMENU
definitions don't work well. Thus, provide an option to override the
defaults in the devicetree.
Writing the OPMENU now happens in ramstage instead of the SMM finalize
handler. If you let coreboot call the finalize handler, nothing should
change. If you call the handler from your payload, OTOH, the OPMENU
might have been changed in between, so be careful what you lock.
Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This moves the sandybridge both smm setup and smihandler code to a
common place.
Tested on Thinkpad X220, still boots, resume to and from S3 is fine
so smihandler is still working fine.
Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).
This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.
Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Boards that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
Removed boards:
amd/dinar
tyan/s2886
supermicro/h8scm
supermicro/h8qgi
Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/amd/geode_gx2
northbridge/amd/gx2
southbridge/amd/cs5535
Mainboards:
mainboard/amd/rumba
mainboard/lippert/frontrunner
mainboard/wyse/s50
Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Use the variable `device` instead of `dev` in the predicate of
the if condition, as `dev` is not changed in the for loop.
The for loop was added in the following commit.
commit 8fed77ae4c46122859d0718678e54546e126d4bc
Author: Scott Duplichan <scott@notabs.org>
Date: Sat Jun 18 10:46:45 2011 -0500
ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
Reviewed-on: http://review.coreboot.org/44
The assumption that the devices are ordered in the tree seem to
hold in this case (although it is not ensured) and therefore at
least with the ASRock E350M1 no (visible) change is experienced as
the children are all of type `DEVICE_PATH_PCI`.
Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Qemu q35 target doesn't support or needs Intel Firmware blobs so
it doesn't make sense to select that option on this hardware.
The result of this change will be that when changing the ROM chip
size, CBFS_SIZE will automatically fill the whole flash which is
desirable in this case.
Change-Id: I89b0c2a7b3e9c163ce4b4eb5b38ab5fa70ba3cfa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23090
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.
This generates the main ACPI _PRT table automatically based on the
chipset registers.
Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
CPU0 CPU1
0: 23 0 IO-APIC 2-edge timer
8: 1 0 IO-APIC 8-edge rtc0
9: 0 0 IO-APIC 9-fasteoi acpi
19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1
23: 0 0 IO-APIC 23-fasteoi i801_smbus
[...MSI and other interrupts skipped...]
Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1
Generated _PRT:
Scope (\_SB.PCI0)
{
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
0x00000000,
0x00000015
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
0x00000000,
0x00000017
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
0x00000000,
0x00000010
}
})
}
Else
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKF,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKH,
0x00000000
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
}
})
}
}
}
Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Based on change I2b5d68adabf0840162c6f295af8d10d8d3007a34
(sb/intel/common: Add function to automatically generate ACPI PIRQ).
This adds functionality to generate PIRQ ACPI tables automatically based
on the chipset registers.
Mapping of PCI interrupt pin to PIRQ is done by the chipset-specific
intel_common_map_pirq() function, an shared implementation of which is
provided for the bd82x6x, i82801, i89xx, ibexpeak and lynxpoint
chipsets.
Example generated _PRT:
Scope (\_SB.PCI0)
{
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
0x00000000,
0x00000010
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
0x00000000,
0x00000015
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
0x00000000,
0x00000013
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
0x00000000,
0x00000011
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
0x00000000,
0x00000017
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
0x00000000,
0x00000010
}
})
}
Else
{
Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001BFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKF,
0x00000000
},
Package (0x04)
{
0x001CFFFF,
0x00000002,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001DFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKD,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKB,
0x00000000
},
Package (0x04)
{
0x001FFFFF,
0x00000001,
\_SB.PCI0.LPCB.LNKH,
0x00000000
},
Package (0x04)
{
0x0004FFFF,
0x00000000,
\_SB.PCI0.LPCB.LNKA,
0x00000000
}
})
}
}
}
Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Removes rs780_before_pci_init() since it was a no-op anyway.
Removes get_nb_rev() since this function is provided via a macro in
the header.
This Makes a lot of function non-static since the header has
prototypes for these.
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This introduces a Kconfig option to include common Intel SPI code.
Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Rework ACPI tables based on a mix of previous work on asus/p2b,
other boards in tree with better ACPI support, and OEM BIOS.
To be pulled in by DSDTs of mainboards using this southbridge.
Disable on-the-fly generation of mainboard _CRS node. It is not working
as it should and causes runtime errors when booting Linux. This node
to be included in mainboard DSDTs in followup patches.
Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The register is 16-bits wide. If the DIR_ROUTE call ordering was
reversed the previous writes would get overwritten.
See page 407ff on the Intel C216 datasheet, which says
"Size: 16bits" with "Default: 3210h" for all DnnIR registers.
This also makes sense given the register offsets:
3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W
[3142h would be D30IR]
3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W
3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W
3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W
314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W
3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W
[discontinuity in register addresses here]
315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W
[315Eh would be D21IR]
3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W
Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
pch_pirq_init() sets all PIRQ links to route to irq 11.
However in the ACPI data, on half the links irq 11 is missing.
The other half is missing irq 10.
This fixes a mostly cosmetic issue in the Linux messages:
ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15)
ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11
ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15)
ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11
ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15)
Change-Id: I002147d702cacf54a233196932b30732f6a433b3
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Replace the unused DTS2 field with FLVL (fan level).
Required to use the fan level on all thinkpads to store and retrieve the
current fan level.
Possible additional use case is to modify the fan level from a SMI handler.
Change-Id: I1ee5348d24b018ab1b61067813c1db63d6706c12
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22513
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
The Infineon TPM chip used on these platforms doesn't use an IRQ
line; the Linux kernel has been patched to work around this, but better
to remove it completely.
Test: boot linux on google/wolf,lulu,cyan without tpm_tis.interrupts=0
kernel parameter, observe no abnormal delays in boot or resume from S3.
Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|