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2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-29Changes to allow Via/Epia code to be compiled after recent code changes.Mark Wilkinson
New Files :- src/cpu/via/model_centaur/Config.lb src/cpu/via/model_centaur/model_centaur_init.c Updated Files :- src/arch/i386/include/arch/smp/mpspec.h - make write_smp_table a define for non smp systems src/cpu/x86/lapic/lapic_cpu_init.c - change possible typo src/mainboard/via/epia/Config.lb src/mainboard/via/epia/Options.lb src/mainboard/via/epia/auto.c src/mainboard/via/epia/chip.h src/mainboard/via/epia/failover.c - updated after recent code changes src/northbridge/via/vt8601/chip.h src/northbridge/via/vt8601/northbridge.c src/northbridge/via/vt8601/raminit.c - corrections after recent code changes to allow compiling src/southbridge/via/vt8231/chip.h src/southbridge/via/vt8231/vt8231.c - initial pass to allow compiling after recent code changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27sizeram removal/conversion.Eric Biederman
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27S2885 winbond Superio all resource setYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22- Better memory I/O space distinguishing in amd_mtrr.cEric Biederman
This is way to much code duplication but for now things work. - Fix the typo in amd8111_lpc.c - Remove an unused macro, use continue instead of break in mtrr.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22- kill typo so resources are not mixed up in amdk8/northbridge.cEric Biederman
- Enable resources on the lpc bus. PCI now longer do this by default for their children unless they are bridges. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21better support enable_dev for amd8111Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- Make all ports use config.h for if they have chip_config or chip_info ↵Eric Biederman
structures. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- Cleanup the bugfix in elfboot.cEric Biederman
- Add forgotten amd8111 chip.h git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30digital logic stuff, fixes for the smbus code in 82801dbmRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-07rename variable from addr to devLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-25changes for the dbm part. Still need to remove the sata file ...Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24compiles.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24new intel io hub.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01Intel E7501 P64H2 ICH5R supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03disable noop usb drivers. remove warningsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-13code reformat, remove BY YHL commentLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-13don't enable VGA/ISA here, it is done in device.c:allocate_vga_resourceLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-13back out immature amd8111_enable stuffLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-10fixed minor bug in APG bridge code. Use AGP_APERTURE_SIZE instead of ↵Li-Ta Lo
IOMMU_APERTURE_SIZE git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-10rename walk_static_devicesLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-07change walk_static_devices() to scan_static_bus()Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-05Disable AMD8111 USB2 and remove hard code addr in amd8111 IDEYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-29changed dev->enable to dev->enabled. Sorry, I am the only one who can't speakLi-Ta Lo
English in the project. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-22start of epia-m portGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-17updatedGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-17get file names rightGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-17start of epia-m portGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-26cleanup code to remove warningsGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-24Further trimming freebios2 towards code reuse.Stefan Reinauer
Unified AMD K8 reset function that can be customized via mainboard Config.lb git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23Doxidization, reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-19simply change for keyboardRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-12fixes for tyanRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11- Moved hlt() to it's own header.Eric Biederman
- Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-09drop dead code.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-02-05enable hpet timer hardware.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-21default values seem to work fineGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-21pass ide base address to driverGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-17*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-17use new pci config setupGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-02fix quartet and S4880 spd initialization.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-02from Yh LuRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-23fixes from SONERonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-22fixes for EPIA.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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