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2013-12-01lynxpoint: Do not clear ACPI NVS region on resumeDuncan Laurie
There are useful values in NVS that are set at boot and runtime and they should not be cleared on resume. suspend/resume twice on slippy and ensure that the USB ports are still powered on the second suspend. Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56941 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-30dmp/vortex86ex: Add timeout for keyboard system flag checking.Andrew Wu
If Vortex86EX PS/2 keyboard controller system flag bit times out, reload controller firmware code and try again. Abort and die after 11 tries as this means the CPU is defect. Also inform the user by printing a message. Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3988 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-30ibexpeak: set HAVE_USBDEBUG_OPTIONSVladimir Serbinenko
Previously, I've set this config in mobo config, yet according to Kyösti Mälkki this parameter is southbridge-specific and not mobo-specific. Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-11-26lynxpoint: Add an inverted input GPIO typeDuncan Laurie
The wake device input pins are active low and the GPIOs need to be set as inverted when they are marked as an input so they are not spuriously logged. suspend/resume on slippy with trackpad wake: 8 | 2013-05-29 07:43:14 | ACPI Enter | S3 9 | 2013-05-29 07:43:18 | ACPI Wake | S3 10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12 and with power button wake: 11 | 2013-05-29 07:43:35 | ACPI Enter | S3 12 | 2013-05-29 07:43:40 | EC Event | Power Button 13 | 2013-05-29 07:43:40 | ACPI Wake | S3 14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0 Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56940 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4209 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25lynxpoint: Enable USB clock gating, late setup, and sleep prepDuncan Laurie
Both EHCI and XHCI controllers have additional setup steps that are not part of the PEI reference code so they need to be done later. Both controllers also have specific clock gating setup requirements that are now implemented. Additionally they both have specific requirements when entering sleep states. XHCI needs something in S3/S4/S5 and EHCI only has steps for S4/S5 entry. Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57033 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4217 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Add ACPI Method to enable GPIO as wake sourceDuncan Laurie
This is an LPT-LP specific method that will enable a specific GPIO as an ACPI SCI wake source. It can be used by a device _DSW method to enable a pin that is otherwise not configured to generate SCI at runtime. It will set: - GPIO owner to ACPI - GPIO route to SCI - GPIO config to GPIO, Input, Inverted Also clean up and remove ACPI field definitions that are unused and/or incorrect. Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56621 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4189 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-25lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQDuncan Laurie
LynxPoint-LP has an additional 16 entries in the IOAPIC that can be assigned to specific GPIOs when they are configured as PIRQ. The maximum redirection entries field in the IOAPIC needs to be set to 0x27 when this is enabled. Additionally specific GPIOs need to be routed to PIRQ so they interrupt via the IOAPIC instead of the GPIO IRQ 14/15. Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56620 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4203 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: fix mem corruption during ssdt2 genAaron Durbin
The ssdt2 generation code was calling acpigen_patch_len(). However, none of the entries had AML object lengths that needed patching. That resulted in the following message: ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c',  line 52 Additionally, this caused an errant write to a memory address whose value was in the variable ltop. This was the 0 address. Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56299 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4182 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Fix XHCI controller device in ACPIDuncan Laurie
The ACPI code was defining two EHCI controllers and ignoring the XHCI controller. This changes the second EHCI controller to be XHCI instead and changes the wake resource to indicate S3 and not S4. cat /proc/acpi/wakeup Device S-state Status Sysfs node HDEF S4 *disabled pci:0000:00:1b.0 EHCI S3 *enabled pci:0000:00:1d.0 XHCI S3 *enabled pci:0000:00:14.0 Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4181 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Enable SerialIO clock in PCI modeDuncan Laurie
The clock gating register at offset 0x800 is managed by the clock driver in the kernel when the devices are in ACPI mode. When in PCI mode we should force enable the clock here. When in ACPI mode or the device is disabled it should be put in D3Hot state. > i2cdetect -y -r 10 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: Enable EC SMIDuncan Laurie
Enable GPIO SMI for GPIO34 and set it as inverted so it is only generated when it is raised by the EC. 1) ec console command: lidopen 2) wait until booted to developer screen 3) ec console command: lidclose 4) ensure system turns off Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56052 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4177 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25lynxpoint: update azalia device idsAaron Durbin
The vendor ids were never updated to reflect LynxPoint's device ids. Therefore, none of the initialization was being ran. Fix this. Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55821 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4173 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Change SerialIO device enable reporting to ACPIDuncan Laurie
In order to report whether coreboot enabled a SerialIO device in ACPI mode we had been relying on reading NVS in the _STA method for the SerialIO device. The ACPI _STA method has restrictions on what it can access and is unable to access OperationRegions outside its scope which means it should not be trying to read NVS. This change adds a new SSDT to the ACPI tables and fills it with constants that indicate whether or not a device is enabled in ACPI mode. The ACPI code is changed to read these variables from the SSDT and use that instead of trying to query a variable in NVS. Attempt to use lpt-clk driver to probe the device clocks for SerialIO devices and see that the kernel does not complain about accessing the GNVS region. Change-Id: I8538bee4390daed4ecca679496ab0cb313f174ce Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51369 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4170 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25slippy: Minor vboot related fixesDuncan Laurie
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Expose ACPI Device for LP GPIO controllerDuncan Laurie
In order to probe the gpio-lynxpoint kernel driver the LP GPIO controller needs to be exposed as a specific ACPI device. This also allows the resources to be exposed to the OS via this device instead of the catch-all LPC device. Ensure the driver loads at boot: gpiochip_find_base: found new base at 162 gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00 Also ensure the driver is visible in sysfs: $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label INT33C7:00 Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50215 Reviewed-on: http://review.coreboot.org/4158 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Move ME lock down to ramstageDuncan Laurie
Now that we have RW ramstage we don't need to have the management engine lock down step done in a final SMM. ME: mkhi_end_of_post ME: END OF POST message successful (0) PCI: 00:16.0: Disabling device Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49757 Reviewed-on: http://review.coreboot.org/4153 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Add missing ME MBP entriesDuncan Laurie
There were two undefined MBP types that are now defined. These include NFC status and some interesting timing data. ME: Wake Event to ME Reset: 6 ms ME: ME Reset to Platform Reset: 7 ms ME: Platform Reset to CPU Reset: 51 ms Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49756 Reviewed-on: http://review.coreboot.org/4152 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: export mem console pointer in ACPIAaron Durbin
Instead of having an OS re-parse cbmem book-keeping records for the cbmem allocator just to get the console buffer export the pointer to the memory console directly in a field named 'CBMC'. This field lives in the GNVS table. Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49764 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4149 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25lynxpoint: Updates to power management and clock gatingDuncan Laurie
Slight tweaks found when looking at latest ref code when investigating package C-state issues. A few bits in the clock gating register don't match the documentation and are also cleaned up. Change-Id: I36ced7280c160b114c70b2eeafc8b24813ff2f6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49330 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4142 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25Support for Ibexpeak southbridgeVladimir Serbinenko
Part of X201 port. Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4052 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-24haswell: Configure PCH power sharing for ULTDuncan Laurie
This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4143 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24lynxpoint: Add a function to set an individual GPIODuncan Laurie
This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24lynxpoint: Rework LP GPIO handlingDuncan Laurie
This adds some macros for the common GPIO defines and drops the gpio number definition from each entry. The end result is much easier to read. The wtm2 mainboard gpio list is modified to use this. Also fix a bug in the LP version of get_gpio() that was always returning zero due to a miscompare. Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4138 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24smi: Update mainboard_smi_gpi() to have 32bit argumentDuncan Laurie
With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Prepare LPC IO decode ranges for ECDuncan Laurie
- 0x200-0x208 for host command window - 0x800-0x8ff for host command arguments and parameters - 0x900-0x9ff for exported EC memory map Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49755 Reviewed-on: http://review.coreboot.org/4151 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24dmp/vortex86ex: Move DMP specific POST code defines into one fileAndrew Wu
Move into src/cpu/dmp/dmp_post_code.h Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3989 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-12AMD Hudson: Move function s3_resume_init_data to southbridgeZheng Bao
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-11-05southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`Paul Menzel
Change-Id: I6bb652419a54b7b7190e417346581f38335425ae Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-30southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy`Paul Menzel
Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail with the following error. src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic': src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Removing `dummy` should be safe as GCC probably optimizes it away before anyway. That no dummy variable is used for an RCBA [1] access in Intel Lynx Point supports that this can be dropped safely. [1] root complex base address [2] src/southbridge/intel/lynxpoint/early_pch.c Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3982 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-22vortex86ex: Defer checking PS/2 keyboard controller system flagAndrew Wu
Don't check keyboard controller system flag until before calling pc_keyboard_init(). This makes waiting time shorter. Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3958 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-22usbdebug: Fix boards without EARLY_CBMEM_INITKyösti Mälkki
The main usbdebug file lib/usbdebug.c was removed from romstage build with commit f8bf5a10 but the chipset-specific parts were not, leading to unresolved symbol errors for AMD platforms. Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient use of this feature. Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3983 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15intel/i82371: Remove HAVE_ACPI_RESUMEKyösti Mälkki
This is needed to apply a rule that get_top_of_ram() in romstage is required to select HAVE_ACPI_RESUME, otherwise chipset/board has no means to backup low memory to CBMEM on s3 resume. Only board affected is asus/p2b. Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3971 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1Jonathan A. Kollasch
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000 (that is, outside the range of bus 0 address space). This causes IOAPIC interrupts to fail to work under Linux. This issue was originally unnoticed by me when testing as sanity checking such as this is not done by NetBSD. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked. Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14ck804: obtain stored IOAPIC address from allocator instead of registerJonathan A. Kollasch
Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3961 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13dmp/vortex86ex: Initialize PS/2 keyboard.Andrew Wu
Call pc_keyboard_init function in southbridge. It makes PS/2 keyboard work in coreinfo payload. Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3957 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14Jonathan A. Kollasch
Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-10-01qemu: q35: avoid address conflictGerd Hoffmann
Qemu has the fw_cfg interface at 0x510, which conflicts with power management base address in coreboot. Move the pmbase to a non-conflicting address. No need to worry about speedstep, it is not supported by qemu and isn't enabled in the qemu config. Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-25usbdebug AMD: Add choice of EHCI controllerKyösti Mälkki
Chipsets sb700 and sb800/hudson have more than one USB EHCI controller, implement the selection logic using already existing Kconfig option. Change-Id: I9e0df1669d73863c95c36a3a7fee40d58f6f097e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-21timestamps intel: Move timestamp scratchpad to chipsetKyösti Mälkki
This retrieves back the value stored with store_initial_timestamp() in the bootblock for southbridge. Change-Id: I377c823706c33ed65af023d20d2e4323edd31199 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3908 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM: Backup top_of_ram instead of cbmem_tocKyösti Mälkki
AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10intel/i945 intel/i82801gx: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3811 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10intel/i82801ix: remove explicit pcie config accessesKyösti Mälkki
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-06usbdebug: Fixes for LynxPoint LPKyösti Mälkki
Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29intel usbdebug: Add choice of EHCI controllerKyösti Mälkki
Add option to choose one of the EHCI controllers in recent intel chipsets for usbdebug use. Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in rcba_config() for some mainboards, check the PCI class code for match. Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Support choice of EHCI controllerKyösti Mälkki
Nowadays, chipsets or boards do not only have one USB port with the capabilities of a debug port but several ones. Some of these ports are easier accessible than others, so making them configurable is also necessary. This change adds infrastructure to switch between EHCI controllers, but does not implement it for any chipset. Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3438 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29usbdebug: Change debug port scanningKyösti Mälkki
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan all physical ports one after other in incrementing order. To avoid possible problems with other USB devices, one can select the port number here and bypass the scan. Intel platforms can communicate with usbdebug dongle on one physical port only, and this option makes no difference there. Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3872 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-27AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in YangtzeWANG Siyuan
src/southbridge/amd/agesa/hudson/Kconfig config default value, mainboard Kconfig config value for specific mainboard. bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3 Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3879 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-24usbdebug: Change reference to EHCI BARKyösti Mälkki
Change the defines, as follow-up patch will replace use of constant CONFIG_EHCI_BAR. Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3875 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 23:17:48 +0000